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Searched refs:pll3_cfg (Results 1 – 6 of 6) sorted by relevance

/u-boot/arch/arm/mach-sunxi/
A Dclock_sun6i.c161 clrbits_le32(&ccm->pll3_cfg, CCM_PLL3_CTRL_EN); in clock_set_pll3()
168 &ccm->pll3_cfg); in clock_set_pll3()
180 &ccm->pll3_cfg); in clock_set_pll3_factors()
182 while (!(readl(&ccm->pll3_cfg) & CCM_PLL3_CTRL_LOCK)) in clock_set_pll3_factors()
305 uint32_t rval = readl(&ccm->pll3_cfg); in clock_get_pll3()
A Dclock_sun4i.c188 clrbits_le32(&ccm->pll3_cfg, CCM_PLL3_CTRL_EN); in clock_set_pll3()
194 CCM_PLL3_CTRL_M(clk / 3000000), &ccm->pll3_cfg); in clock_set_pll3()
201 uint32_t rval = readl(&ccm->pll3_cfg); in clock_get_pll3()
/u-boot/arch/arm/include/asm/arch-sunxi/
A Dclock_sun8i_a83t.h21 u32 pll3_cfg; /* 0x10 pll3 video0 control */ member
A Dclock_sun4i.h18 u32 pll3_cfg; /* 0x10 pll3 control */ member
A Dclock_sun50i_h6.h27 u32 pll3_cfg; /* 0x040 pll3 (video0) control */ member
A Dclock_sun6i.h18 u32 pll3_cfg; /* 0x10 pll3 control */ member

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