Home
last modified time | relevance | path

Searched refs:pll6_cfg (Results 1 – 8 of 8) sorted by relevance

/u-boot/arch/arm/mach-sunxi/
A Dclock_sun50i_h6.c19 writel(CCM_PLL6_DEFAULT, &ccm->pll6_cfg); in clock_init_safe()
20 while (!(readl(&ccm->pll6_cfg) & CCM_PLL6_LOCK)) in clock_init_safe()
96 uint32_t rval = readl(&ccm->pll6_cfg); in clock_get_pll6()
A Dclock_sun8i_a83t.c40 writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg); in clock_init_safe()
129 uint32_t rval = readl(&ccm->pll6_cfg); in clock_get_pll6()
A Dclock_sun4i.c40 writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg); in clock_init_safe()
43 setbits_le32(&ccm->pll6_cfg, 0x1 << CCM_PLL6_CTRL_SATA_EN_SHIFT); in clock_init_safe()
221 uint32_t rval = readl(&ccm->pll6_cfg); in clock_get_pll6()
A Dclock_sun6i.c46 writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg); in clock_init_safe()
47 while (!(readl(&ccm->pll6_cfg) & CCM_PLL6_CTRL_LOCK)) in clock_init_safe()
317 uint32_t rval = readl(&ccm->pll6_cfg); in clock_get_pll6()
/u-boot/arch/arm/include/asm/arch-sunxi/
A Dclock_sun8i_a83t.h27 u32 pll6_cfg; /* 0x28 pll6 peripheral control */ member
A Dclock_sun4i.h24 u32 pll6_cfg; /* 0x28 pll6 control */ member
A Dclock_sun50i_h6.h21 u32 pll6_cfg; /* 0x020 pll6 (periph0) control */ member
A Dclock_sun6i.h24 u32 pll6_cfg; /* 0x28 pll6 control */ member

Completed in 17 milliseconds