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Searched refs:pll_cfg0 (Results 1 – 1 of 1) sorted by relevance

/u-boot/arch/arm/mach-imx/imx8m/
A Dclock_imx8mq.c24 u32 pll_cfg0, pll_cfg1, pllout; in decode_frac_pll() local
31 pll_cfg0 = readl(&ana_pll->arm_pll_cfg0); in decode_frac_pll()
45 if (pll_cfg0 & FRAC_PLL_PD_MASK) in decode_frac_pll()
49 if ((pll_cfg0 & FRAC_PLL_CLKE_MASK) == 0) in decode_frac_pll()
63 if (pll_cfg0 & FRAC_PLL_BYPASS_MASK) in decode_frac_pll()
84 u32 pll_cfg0, pll_cfg1, pll_cfg2; in decode_sscg_pll() local
202 if (pll_cfg0 & SSCG_PLL_PD_MASK) in decode_sscg_pll()
206 if ((pll_cfg0 & pll_clke) == 0) in decode_sscg_pll()
225 (pll_cfg0 & SSCG_PLL_BYPASS2_MASK)) in decode_sscg_pll()
664 pll_cfg0 = &ana_pll->arm_pll_cfg0; in frac_pll_init()
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