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/u-boot/arch/arm/mach-imx/imx8m/
A Dclock_imx8mq.c84 u32 pll_cfg0, pll_cfg1, pll_cfg2; in decode_sscg_pll() local
104 pll_cfg2 = readl(&ana_pll->sys_pll1_cfg2); in decode_sscg_pll()
119 pll_cfg2 = readl(&ana_pll->sys_pll2_cfg2); in decode_sscg_pll()
126 pll_cfg2 = readl(&ana_pll->sys_pll3_cfg2); in decode_sscg_pll()
133 pll_cfg2 = readl(&ana_pll->dram_pll_cfg2); in decode_sscg_pll()
228 divr1 = (pll_cfg2 & SSCG_PLL_REF_DIVR1_MASK) >> in decode_sscg_pll()
230 divr2 = (pll_cfg2 & SSCG_PLL_REF_DIVR2_MASK) >> in decode_sscg_pll()
232 divf1 = (pll_cfg2 & SSCG_PLL_FEEDBACK_DIV_F1_MASK) >> in decode_sscg_pll()
234 divf2 = (pll_cfg2 & SSCG_PLL_FEEDBACK_DIV_F2_MASK) >> in decode_sscg_pll()
236 divq = (pll_cfg2 & SSCG_PLL_OUTPUT_DIV_VAL_MASK) >> in decode_sscg_pll()

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