Searched refs:pll_config (Results 1 – 7 of 7) sorted by relevance
| /u-boot/drivers/clk/renesas/ |
| A D | clk-rcar-gen3.c | 164 const struct rcar_gen3_cpg_pll_config *pll_config = in gen3_clk_get_rate64() local
208 rate = gen3_clk_get_rate64(&parent) / pll_config->extal_div; in gen3_clk_get_rate64()
211 core->parent, pll_config->extal_div, rate); in gen3_clk_get_rate64()
223 rate = gen3_clk_get_rate64(&parent) * pll_config->pll1_mult; in gen3_clk_get_rate64()
224 rate /= pll_config->pll1_div; in gen3_clk_get_rate64()
227 core->parent, pll_config->pll1_mult, in gen3_clk_get_rate64()
228 pll_config->pll1_div, rate); in gen3_clk_get_rate64()
240 rate = gen3_clk_get_rate64(&parent) * pll_config->pll3_mult; in gen3_clk_get_rate64()
241 rate /= pll_config->pll3_div; in gen3_clk_get_rate64()
244 core->parent, pll_config->pll3_mult, in gen3_clk_get_rate64()
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| A D | clk-rcar-gen2.c | 82 const struct rcar_gen2_cpg_pll_config *pll_config = in gen2_clk_get_rate() local
140 rate = gen2_clk_get_rate(&parent) / pll_config->extal_div; in gen2_clk_get_rate()
143 core->parent, pll_config->extal_div, rate); in gen2_clk_get_rate()
153 mult = pll_config->pll0_mult; in gen2_clk_get_rate()
165 rate = (gen2_clk_get_rate(&parent) * pll_config->pll1_mult) / 2; in gen2_clk_get_rate()
168 core->parent, pll_config->pll1_mult, rate); in gen2_clk_get_rate()
172 rate = gen2_clk_get_rate(&parent) * pll_config->pll3_mult; in gen2_clk_get_rate()
175 core->parent, pll_config->pll3_mult, rate); in gen2_clk_get_rate()
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| /u-boot/drivers/video/ |
| A D | ssd2828.c | 279 static u32 decode_pll_config(u32 pll_config, u32 reference_freq_khz) in decode_pll_config() argument
281 u32 mul_factor = pll_config & 0xFF; in decode_pll_config()
282 u32 div_factor = (pll_config >> 8) & 0x1F; in decode_pll_config()
344 u32 lp_div, pll_freq_kbps, reference_freq_khz, pll_config; in ssd2828_init() local
406 pll_config = construct_pll_config( in ssd2828_init()
409 write_hw_register(cfg, SSD2828_PLCR, pll_config); in ssd2828_init()
411 pll_freq_kbps = decode_pll_config(pll_config, reference_freq_khz); in ssd2828_init()
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| /u-boot/arch/arm/mach-omap2/am33xx/ |
| A D | clock_ti814x.c | 224 static void pll_config(u32 base, u32 n, u32 m, u32 m2, in pll_config() function
309 pll_config(MPU_PLL_BASE, MPU_N, MPU_M, MPU_M2, MPU_CLKCTRL, 0); in mpu_pll_config()
324 pll_config(L3_PLL_BASE, L3_N, L3_M, L3_M2, L3_CLKCTRL, 1); in l3_pll_config()
329 pll_config(DDR_PLL_BASE, DDR_N, DDR_M, DDR_M2, DDR_CLKCTRL, 1); in ddr_pll_config()
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| /u-boot/arch/arm/mach-socfpga/ |
| A D | qts-filter.sh | 117 ${in_bsp_dir}/generated/pll_config.h |
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| /u-boot/doc/ |
| A D | README.socfpga | 131 pll_config.h
143 -rw-r--r-- 1 sarnold sarnold 3190 Mar 21 18:11 pll_config.h
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| /u-boot/drivers/clk/ |
| A D | clk_stm32mp1.c | 1623 static int pll_config(struct stm32mp1_clk_priv *priv, int pll_id, in pll_config() function
1745 pll_config(priv, pll_id, pllcfg, fracv); in pll_set_rate()
2030 pll_config(priv, i, pllcfg[i], pllfracv[i]); in stm32mp1_clktree()
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