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Searched refs:pll_div (Results 1 – 18 of 18) sorted by relevance

/u-boot/arch/arm/mach-nexell/
A Dclock.c362 static unsigned int pll_div(int dvo) in pll_div() function
374 ((pll_div(n) >> 0) & 0x3F))
377 ((pll_div(n) >> 8) & 0x3F))
381 ((pll_div(DIV_MEM) >> 8) & 0x3F))
384 ((pll_div(DIV_MEM) >> 0) & 0x3F))
389 ((pll_div(DIV_MEM) >> 16) & 0x3F))
394 ((pll_div(DIV_MEM) >> 24) & 0x3F))
397 ((pll_div(DIV_BUS) >> 0) & 0x3F))
400 ((pll_div(DIV_BUS) >> 8) & 0x3F))
403 ((pll_div(DIV_G3D) >> 0) & 0x3F))
[all …]
/u-boot/drivers/clk/imx/
A Dclk-pll14xx.c72 u32 mdiv, pdiv, sdiv, pll_div; in clk_pll1416x_recalc_rate() local
74 pll_div = readl(pll->base + 4); in clk_pll1416x_recalc_rate()
75 mdiv = (pll_div & MDIV_MASK) >> MDIV_SHIFT; in clk_pll1416x_recalc_rate()
76 pdiv = (pll_div & PDIV_MASK) >> PDIV_SHIFT; in clk_pll1416x_recalc_rate()
77 sdiv = (pll_div & SDIV_MASK) >> SDIV_SHIFT; in clk_pll1416x_recalc_rate()
109 u32 pll_div) in clk_pll1416x_mp_change() argument
113 old_mdiv = (pll_div & MDIV_MASK) >> MDIV_SHIFT; in clk_pll1416x_mp_change()
114 old_pdiv = (pll_div & PDIV_MASK) >> PDIV_SHIFT; in clk_pll1416x_mp_change()
/u-boot/drivers/clk/rockchip/
A Dclk_rk3368.c34 struct pll_div { struct
55 static const struct pll_div apll_l_init_cfg = PLL_DIVISORS(APLL_L_HZ, 12, 2); argument
56 static const struct pll_div apll_b_init_cfg = PLL_DIVISORS(APLL_B_HZ, 1, 2);
58 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 1, 2);
59 static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 6);
94 const struct pll_div *div) in rkclk_set_pll()
289 const struct pll_div *dpll_cfg = NULL; in rk3368_ddr_set_clk()
293 static const struct pll_div dpll_1200 = PLL_DIVISORS(1200 * MHz, 1, 1); in rk3368_ddr_set_clk()
294 static const struct pll_div dpll_1332 = PLL_DIVISORS(1332 * MHz, 2, 1); in rk3368_ddr_set_clk()
295 static const struct pll_div dpll_1600 = PLL_DIVISORS(1600 * MHz, 3, 2); in rk3368_ddr_set_clk()
A Dclk_rk3399.c40 struct pll_div { struct
66 static const struct pll_div *apll_l_cfgs[] = {
684 struct pll_div vpll_config = {0}; in rk3399_vop_set_clk()
834 struct pll_div dpll_cfg; in rk3399_ddr_set_clk()
842 dpll_cfg = (struct pll_div) in rk3399_ddr_set_clk()
846 dpll_cfg = (struct pll_div) in rk3399_ddr_set_clk()
850 dpll_cfg = (struct pll_div) in rk3399_ddr_set_clk()
854 dpll_cfg = (struct pll_div) in rk3399_ddr_set_clk()
858 dpll_cfg = (struct pll_div) in rk3399_ddr_set_clk()
862 dpll_cfg = (struct pll_div) in rk3399_ddr_set_clk()
[all …]
A Dclk_rk322x.c44 static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 3, 1);
45 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1);
48 const struct pll_div *div) in rkclk_set_pll()
327 struct pll_div dpll_cfg; in rk322x_ddr_set_clk()
332 dpll_cfg = (struct pll_div) in rk322x_ddr_set_clk()
336 dpll_cfg = (struct pll_div) in rk322x_ddr_set_clk()
340 dpll_cfg = (struct pll_div) in rk322x_ddr_set_clk()
A Dclk_rk3328.c25 struct pll_div { struct
42 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 1, 4, 1); argument
43 static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 2, 2, 1);
45 static const struct pll_div apll_816_cfg = PLL_DIVISORS(816 * MHz, 1, 2, 1);
46 static const struct pll_div apll_600_cfg = PLL_DIVISORS(600 * MHz, 1, 3, 1);
48 static const struct pll_div *apll_cfgs[] = {
212 const struct pll_div *div) in rkclk_set_pll()
A Dclk_rk3188.c41 struct pll_div { struct
86 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2);
87 static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2);
91 const struct pll_div *div, bool has_bwadj) in rkclk_set_pll()
127 static const struct pll_div dpll_cfg[] = { in rkclk_configure_ddr()
173 static const struct pll_div apll_cfg[] = { in rkclk_configure_cpu()
A Dclk_rk3288.c41 struct pll_div { struct
147 static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 1);
148 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2);
149 static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2);
152 const struct pll_div *div) in rkclk_set_pll()
185 static const struct pll_div dpll_cfg[] = { in rkclk_configure_ddr()
234 static int pll_para_config(ulong freq_hz, struct pll_div *div, uint *ext_div) in pll_para_config()
346 struct pll_div npll_config = {0}; in rockchip_vop_set_clk()
A Dclk_rk3128.c39 static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 3, 1);
40 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1);
43 const struct pll_div *div) in rkclk_set_pll()
80 static int pll_para_config(u32 freq_hz, struct pll_div *div) in pll_para_config()
423 struct pll_div cpll_config = {0}; in rk3128_vop_set_clk()
A Dclk_rk3036.c46 static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 3, 1);
47 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1);
50 const struct pll_div *div) in rkclk_set_pll()
A Dclk_rv1108.c46 static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 3, 1);
47 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1);
72 const struct pll_div *div) in rkclk_set_pll()
/u-boot/arch/arm/mach-imx/mx7/
A Dclock.c779 static int enable_pll_video(u32 pll_div, u32 pll_num, u32 pll_denom, in enable_pll_video() argument
786 pll_div, pll_num, pll_denom); in enable_pll_video()
800 writel(CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT(pll_div) | in enable_pll_video()
806 writel(CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT(pll_div) | in enable_pll_video()
812 writel(CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT(pll_div) | in enable_pll_video()
818 writel(CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT(pll_div) | in enable_pll_video()
825 writel(CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT(pll_div) | in enable_pll_video()
902 u32 pll_div, pll_num, pll_denom, post_div = 0; in mxs_set_lcdclk() local
946 pll_div = best / hck; in mxs_set_lcdclk()
948 pll_num = (best - hck * pll_div) * pll_denom / hck; in mxs_set_lcdclk()
[all …]
/u-boot/arch/arm/mach-imx/mx6/
A Dclock.c553 static int enable_pll_video(u32 pll_div, u32 pll_num, u32 pll_denom, in enable_pll_video() argument
560 pll_div, pll_num, pll_denom); in enable_pll_video()
572 writel(BF_ANADIG_PLL_VIDEO_DIV_SELECT(pll_div) | in enable_pll_video()
577 writel(BF_ANADIG_PLL_VIDEO_DIV_SELECT(pll_div) | in enable_pll_video()
582 writel(BF_ANADIG_PLL_VIDEO_DIV_SELECT(pll_div) | in enable_pll_video()
628 u32 pll_div, pll_num, pll_denom, post_div = 1; in mxs_set_lcdclk() local
699 pll_div = best / hck; in mxs_set_lcdclk()
701 pll_num = (best - hck * pll_div) * pll_denom / hck; in mxs_set_lcdclk()
712 if (enable_pll_video(pll_div, pll_num, pll_denom, post_div)) in mxs_set_lcdclk()
749 if (enable_pll_video(pll_div, pll_num, pll_denom, post_div)) in mxs_set_lcdclk()
/u-boot/arch/arm/include/asm/arch-rockchip/
A Dcru_rk3036.h58 struct pll_div { struct
A Dcru_rk3128.h65 struct pll_div { struct
A Dcru_rk322x.h59 struct pll_div { struct
A Dcru_rv1108.h55 struct pll_div { struct
/u-boot/arch/arm/mach-rockchip/rk3036/
A Dsdram_rk3036.c41 const struct pll_div dpll_init_cfg = {1, 66, 2, 1};

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