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Searched refs:pll_refclk_sel (Results 1 – 1 of 1) sorted by relevance

/u-boot/arch/arm/mach-imx/imx8m/
A Dclock_imx8mq.c25 u32 pll_refclk_sel, pll_refclk; in decode_frac_pll() local
52 pll_refclk_sel = pll_cfg0 & FRAC_PLL_REFCLK_SEL_MASK; in decode_frac_pll()
54 if (pll_refclk_sel == FRAC_PLL_REFCLK_SEL_OSC_25M) in decode_frac_pll()
56 else if (pll_refclk_sel == FRAC_PLL_REFCLK_SEL_OSC_27M) in decode_frac_pll()
58 else if (pll_refclk_sel == FRAC_PLL_REFCLK_SEL_HDMI_PHY_27M) in decode_frac_pll()
85 u32 pll_refclk_sel, pll_refclk; in decode_sscg_pll() local
212 pll_refclk_sel = pll_cfg0 & SSCG_PLL_REFCLK_SEL_MASK; in decode_sscg_pll()
214 if (pll_refclk_sel == SSCG_PLL_REFCLK_SEL_OSC_25M) in decode_sscg_pll()
216 else if (pll_refclk_sel == SSCG_PLL_REFCLK_SEL_OSC_27M) in decode_sscg_pll()
218 else if (pll_refclk_sel == SSCG_PLL_REFCLK_SEL_HDMI_PHY_27M) in decode_sscg_pll()

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