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Searched refs:pll_regs (Results 1 – 8 of 8) sorted by relevance

/u-boot/arch/arm/cpu/arm926ejs/mx27/
A Dgeneric.c48 struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE; in clk_in_26m()
60 struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE; in imx_get_mpllclk()
74 struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE; in imx_get_armclk()
89 struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE; in imx_get_ahbclk()
101 struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE; in imx_get_spllclk()
120 struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE; in imx_get_perclk1()
127 struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE; in imx_get_perclk2()
134 struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE; in imx_get_perclk3()
141 struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE; in imx_get_perclk4()
183 struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE; in cpu_eth_init()
A Dtimer.c96 struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE; in timer_init()
/u-boot/arch/mips/mach-ath79/ar934x/
A Dclk.c113 void __iomem *pll_regs = map_physmem(AR71XX_PLL_BASE, in ar934x_pll_init() local
173 setbits_be32(pll_regs + AR934X_PLL_CPU_DDR_CLK_CTRL_REG, in ar934x_pll_init()
175 setbits_be32(pll_regs + AR934X_PLL_CPU_DDR_CLK_CTRL_REG, in ar934x_pll_init()
177 setbits_be32(pll_regs + AR934X_PLL_CPU_DDR_CLK_CTRL_REG, in ar934x_pll_init()
182 pll_regs + AR934X_PLL_CPU_CONFIG_REG); in ar934x_pll_init()
185 pll_regs + AR934X_PLL_DDR_CONFIG_REG); in ar934x_pll_init()
196 pll_regs + AR934X_PLL_CPU_DDR_CLK_CTRL_REG); in ar934x_pll_init()
203 clrbits_be32(pll_regs + AR934X_PLL_CPU_DDR_CLK_CTRL_REG, in ar934x_pll_init()
205 clrbits_be32(pll_regs + AR934X_PLL_CPU_DDR_CLK_CTRL_REG, in ar934x_pll_init()
213 pll_regs + AR934X_PLL_DDR_DIT_FRAC_REG); in ar934x_pll_init()
[all …]
/u-boot/arch/mips/mach-ath79/qca956x/
A Dclk.c188 void __iomem *pll_regs = map_physmem(AR71XX_PLL_BASE, in set_val() local
190 writel((readl(pll_regs + _reg) & (~(_mask))) | _val, pll_regs + _reg); in set_val()
224 void __iomem *pll_regs = map_physmem(AR71XX_PLL_BASE, in qca956x_pll_init() local
277 CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_SET(1), pll_regs + QCA956X_PLL_CLK_CTRL_REG); in qca956x_pll_init()
280 writel(DDR_PLL_DITHER1_VAL, pll_regs + QCA956X_PLL_DDR_DIT_FRAC_REG); in qca956x_pll_init()
281 writel(DDR_PLL_DITHER2_VAL, pll_regs + QCA956X_PLL_DDR_DIT2_FRAC_REG); in qca956x_pll_init()
284 writel(CPU_PLL_DITHER1_VAL, pll_regs + QCA956X_PLL_CPU_DIT_FRAC_REG); in qca956x_pll_init()
285 writel(CPU_PLL_DITHER2_VAL, pll_regs + QCA956X_PLL_CPU_DIT2_FRAC_REG); in qca956x_pll_init()
303 while (readl(pll_regs + QCA956X_PLL_CPU_CONFIG_REG) & 0x8000000) in qca956x_pll_init()
306 while (readl(pll_regs + QCA956X_PLL_DDR_CONFIG_REG) & 0x8000000) in qca956x_pll_init()
/u-boot/arch/arm/lib/
A Dasm-offsets.c80 DEFINE(CSCR, IMX_PLL_BASE + offsetof(struct pll_regs, cscr)); in main()
81 DEFINE(MPCTL0, IMX_PLL_BASE + offsetof(struct pll_regs, mpctl0)); in main()
82 DEFINE(SPCTL0, IMX_PLL_BASE + offsetof(struct pll_regs, spctl0)); in main()
83 DEFINE(PCDR0, IMX_PLL_BASE + offsetof(struct pll_regs, pcdr0)); in main()
84 DEFINE(PCDR1, IMX_PLL_BASE + offsetof(struct pll_regs, pcdr1)); in main()
85 DEFINE(PCCR0, IMX_PLL_BASE + offsetof(struct pll_regs, pccr0)); in main()
86 DEFINE(PCCR1, IMX_PLL_BASE + offsetof(struct pll_regs, pccr1)); in main()
/u-boot/board/armadeus/apf27/
A Dfpga.c195 struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE; in apf27_fpga_setup()
/u-boot/drivers/clk/
A Dclk-hsdk-cgu.c236 void __iomem *pll_regs; member
379 iowrite32(val, clk->curr_domain.pll_regs + reg); in hsdk_pll_write()
384 return ioread32(clk->curr_domain.pll_regs + reg); in hsdk_pll_read()
694 clk->curr_domain.pll_regs = clk->cgu_regs + clk->map[sclk->id].cgu_pll_oft; in hsdk_prepare_clock_tree_branch()
/u-boot/arch/arm/include/asm/arch-mx27/
A Dimx-regs.h114 struct pll_regs { struct

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