Searched refs:pllckselr (Results 1 – 1 of 1) sorted by relevance

/u-boot/drivers/clk/
A D	clk_stm32h7.c	135 u32 pllckselr; /* 0x28 PLLs Clock Source Selection Register */ member 355 uint32_t pllckselr = 0; in configure_clocks() local 398 pllckselr |= RCC_PLLCKSELR_PLLSRC_HSE; in configure_clocks() 399 pllckselr |= sys_pll_psc.divm << RCC_PLLCKSELR_DIVM1_SHIFT; in configure_clocks() 400 writel(pllckselr, &regs->pllckselr); in configure_clocks() 509 switch (readl(&regs->pllckselr) & RCC_PLLCKSELR_PLLSRC_MASK) { in stm32_get_PLL1_rate() 531 divm1 = readl(&regs->pllckselr) & RCC_PLLCKSELR_DIVM1_MASK; in stm32_get_PLL1_rate()

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