Searched refs:pllcr0 (Results 1 – 12 of 12) sorted by relevance
233 pll_status = in_be32(&srds_regs->bank[pll_num].pllcr0); in serdes_init()277 pll_cr0 = in_be32(&srds_regs->bank[pll_num].pllcr0); in serdes_init()278 out_be32(&srds_regs->bank[pll_num].pllcr0, in serdes_init()304 pll_cr0 = in_be32(&srds_regs->bank[pll_num].pllcr0); in serdes_init()305 out_be32(&srds_regs->bank[pll_num].pllcr0, pll_cr0 | in serdes_init()311 pll_cr0 = in_be32(&srds_regs->bank[pll_num].pllcr0); in serdes_init()312 out_be32(&srds_regs->bank[pll_num].pllcr0, pll_cr0 & in serdes_init()320 pll_status = in_be32(&srds_regs->bank[pll_num].pllcr0); in serdes_init()
404 clrsetbits_be32(®s->bank[FSL_SRDS_BANK_3].pllcr0, in p4080_erratum_serdes8()407 clrsetbits_be32(®s->bank[FSL_SRDS_BANK_3].pllcr0, in p4080_erratum_serdes8()683 setbits_be32(&srds_regs->bank[bank].pllcr0, in fsl_serdes_init()
322 reg = in_be32(&serdes1_base->bank[i].pllcr0); in setup_serdes_volt()341 reg = in_be32(&serdes2_base->bank[i].pllcr0); in setup_serdes_volt()382 reg = in_be32(&serdes1_base->bank[i].pllcr0); in setup_serdes_volt()393 reg = in_be32(&serdes2_base->bank[i].pllcr0); in setup_serdes_volt()
351 reg = in_le32(&serdes_base->bank[i].pllcr0); in do_pll_reset_done()383 reg = in_le32(&serdes_base->bank[i].pllcr0); in do_pll_lock()
147 u32 actual = in_be32(®s->bank[i].pllcr0); in misc_init_r()
179 u32 expected = srds_regs->bank[i].pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK; in misc_init_r()
206 u32 expected = in_be32(®s->bank[i].pllcr0); in misc_init_r()
231 u32 actual = in_be32(®s->bank[USED_SRDS_BANK].pllcr0); in misc_init_r()
345 u32 pllcr0; /* PLL Control Register 0 */ member
561 u32 pllcr0; /* PLL Control Register 0 */ member
573 u32 pllcr0; /* PLL Control Register 0 */ member
2535 u32 pllcr0; /* PLL Control Register 0 */ member2619 u32 pllcr0; /* PLL Control Register 0 */ member
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