Searched refs:pllcr1 (Results 1 – 6 of 6) sorted by relevance
268 pll_cr1 = in_be32(&srds_regs->bank[pll_num].pllcr1); in serdes_init()271 out_be32(&srds_regs->bank[pll_num].pllcr1, in serdes_init()285 pll_cr1 = in_be32(&srds_regs->bank[pll_num].pllcr1); in serdes_init()287 out_be32(&srds_regs->bank[pll_num].pllcr1, in serdes_init()
375 setbits_be32(®s->bank[FSL_SRDS_BANK_3].pllcr1, in p4080_erratum_serdes8()433 clrbits_be32(®s->bank[FSL_SRDS_BANK_1].pllcr1, in p4080_erratum_serdes_a005()441 clrbits_be32(®s->bank[FSL_SRDS_BANK_1].pllcr1, in p4080_erratum_serdes_a005()443 setbits_be32(®s->bank[FSL_SRDS_BANK_3].pllcr1, in p4080_erratum_serdes_a005()456 clrbits_be32(®s->bank[bank].pllcr1, in p4080_erratum_serdes_a005()
347 u32 pllcr1; /* PLL Control Register 1 */ member
562 u32 pllcr1; /* PLL Control Register 1 */ member
590 u32 pllcr1; /* PLL Control Register 1 */ member
2557 u32 pllcr1; /* PLL Control Register 1 */ member2630 u32 pllcr1; /* PLL Control Register 1 */ member
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