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Searched refs:pllinfo (Results 1 – 7 of 7) sorted by relevance

/u-boot/arch/arm/mach-tegra/
A Dclock.c105 *divm = (data >> pllinfo->m_shift) & pllinfo->m_mask; in clock_ll_read_pll()
106 *divn = (data >> pllinfo->n_shift) & pllinfo->n_mask; in clock_ll_read_pll()
107 *divp = (data >> pllinfo->p_shift) & pllinfo->p_mask; in clock_ll_read_pll()
110 *cpcon = (data >> pllinfo->kcp_shift) & pllinfo->kcp_mask; in clock_ll_read_pll()
111 *lfcon = (data >> pllinfo->kvco_shift) & pllinfo->kvco_mask; in clock_ll_read_pll()
145 misc_data &= ~(pllinfo->kcp_mask << pllinfo->kcp_shift); in clock_start_pll()
147 misc_data &= ~(pllinfo->kvco_mask << pllinfo->kvco_shift); in clock_start_pll()
556 divm = (base >> pllinfo->m_shift) & pllinfo->m_mask; in clock_get_rate()
603 base_reg &= ~(pllinfo->m_mask << pllinfo->m_shift); in clock_set_rate()
606 base_reg &= ~(pllinfo->n_mask << pllinfo->n_shift); in clock_set_rate()
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A Dcpu.c175 struct clk_pll_info *pllinfo = &tegra_pll_info_table[CLOCK_ID_XCPU]; in pllx_set_rate() local
189 reg = PLL_BYPASS_MASK | (divm << pllinfo->m_shift); in pllx_set_rate()
190 reg |= (divn << pllinfo->n_shift) | (divp << pllinfo->p_shift); in pllx_set_rate()
195 reg = (cpcon << pllinfo->kcp_shift); in pllx_set_rate()
216 if (pllinfo->lock_ena < 32) in pllx_set_rate()
217 reg |= (1 << pllinfo->lock_ena); in pllx_set_rate()
/u-boot/arch/arm/mach-tegra/tegra114/
A Dclock.c661 struct clk_pll_info *pllinfo; in clock_early_init() local
667 pllinfo = &tegra_pll_info_table[CLOCK_ID_CGENERAL]; in clock_early_init()
704 pllinfo = &tegra_pll_info_table[CLOCK_ID_CGENERAL]; in clock_early_init()
705 setbits_le32(&clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_misc, (1 << pllinfo->lock_ena)); in clock_early_init()
709 pllinfo = &tegra_pll_info_table[CLOCK_ID_DISPLAY]; in clock_early_init()
710 data = (12 << pllinfo->kcp_shift) | (1 << pllinfo->kvco_shift); in clock_early_init()
711 data |= (1 << PLLD_CLKENABLE) | (1 << pllinfo->lock_ena); in clock_early_init()
A Dcpu.c56 struct clk_pll_info *pllinfo = &tegra_pll_info_table[CLOCK_ID_XCPU]; in enable_cpu_clocks() local
64 } while ((reg & (1 << pllinfo->lock_det)) == 0); in enable_cpu_clocks()
/u-boot/arch/arm/mach-tegra/tegra124/
A Dcpu.c49 struct clk_pll_info *pllinfo = &tegra_pll_info_table[CLOCK_ID_XCPU]; in enable_cpu_clocks() local
58 } while ((reg & (1 << pllinfo->lock_det)) == 0); in enable_cpu_clocks()
A Dclock.c841 struct clk_pll_info *pllinfo; in clock_early_init() local
847 pllinfo = &tegra_pll_info_table[CLOCK_ID_CGENERAL]; in clock_early_init()
884 pllinfo = &tegra_pll_info_table[CLOCK_ID_CGENERAL]; in clock_early_init()
885 setbits_le32(&clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_misc, (1 << pllinfo->lock_ena)); in clock_early_init()
889 pllinfo = &tegra_pll_info_table[CLOCK_ID_DISPLAY]; in clock_early_init()
890 data = (12 << pllinfo->kcp_shift) | (1 << pllinfo->kvco_shift); in clock_early_init()
891 data |= (1 << PLLD_CLKENABLE) | (1 << pllinfo->lock_ena); in clock_early_init()
/u-boot/arch/arm/mach-tegra/tegra210/
A Dclock.c978 struct clk_pll_info *pllinfo = &tegra_pll_info_table[CLOCK_ID_DISPLAY]; in clock_early_init() local
1033 data = (1 << PLLD_ENABLE_CLK) | (1 << pllinfo->lock_ena); in clock_early_init()

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