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Searched refs:pllreg (Results 1 – 5 of 5) sorted by relevance

/u-boot/arch/arm/mach-s5pc1xx/
A Dclock.c25 static unsigned long s5pc100_get_pll_clk(int pllreg) in s5pc100_get_pll_clk() argument
32 switch (pllreg) { in s5pc100_get_pll_clk()
46 printf("Unsupported PLL (%d)\n", pllreg); in s5pc100_get_pll_clk()
56 if (pllreg == APLL) in s5pc100_get_pll_clk()
83 switch (pllreg) { in s5pc110_get_pll_clk()
97 printf("Unsupported PLL (%d)\n", pllreg); in s5pc110_get_pll_clk()
107 if (pllreg == APLL || pllreg == MPLL) in s5pc110_get_pll_clk()
120 if (pllreg == APLL) { in s5pc110_get_pll_clk()
297 unsigned long get_pll_clk(int pllreg) in get_pll_clk() argument
300 return s5pc110_get_pll_clk(pllreg); in get_pll_clk()
[all …]
/u-boot/arch/arm/mach-exynos/
A Dclock.c126 if (pllreg == APLL || pllreg == MPLL || pllreg == BPLL || in exynos_get_pll_clk()
127 pllreg == SPLL) in exynos_get_pll_clk()
141 if (pllreg == EPLL || pllreg == RPLL) { in exynos_get_pll_clk()
145 } else if (pllreg == VPLL) { in exynos_get_pll_clk()
192 switch (pllreg) { in exynos4_get_pll_clk()
222 switch (pllreg) { in exynos4x12_get_pll_clk()
253 switch (pllreg) { in exynos5_get_pll_clk()
280 if (pllreg == MPLL || pllreg == BPLL) { in exynos5_get_pll_clk()
283 switch (pllreg) { in exynos5_get_pll_clk()
311 switch (pllreg) { in exynos542x_get_pll_clk()
[all …]
/u-boot/arch/arm/cpu/arm920t/ep93xx/
A Dspeed.c26 static ulong get_PLLCLK(uint32_t *pllreg) in get_PLLCLK() argument
29 const uint32_t clkset = readl(pllreg); in get_PLLCLK()
/u-boot/arch/arm/mach-s5pc1xx/include/mach/
A Dclk.h17 unsigned long get_pll_clk(int pllreg);
/u-boot/arch/arm/mach-exynos/include/mach/
A Dclk.h37 unsigned long get_pll_clk(int pllreg);

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