Searched refs:postdiv (Results 1 – 7 of 7) sorted by relevance
| /u-boot/drivers/clk/mediatek/ |
| A D | clk-mtk.c | 96 u32 fin, u32 pcw, int postdiv) in __mtk_pll_recalc_rate() argument
118 return ((unsigned long)vco + postdiv - 1) / postdiv; in __mtk_pll_recalc_rate()
136 val |= (ffs(postdiv) - 1) << pll->pd_shift; in mtk_pll_set_rate_regs()
182 *postdiv = 1 << val; in mtk_pll_calc_values()
183 if ((u64)freq * *postdiv >= fmin) in mtk_pll_calc_values()
198 u32 postdiv; in mtk_apmixedsys_set_rate() local
200 mtk_pll_calc_values(clk, &pcw, &postdiv, rate); in mtk_apmixedsys_set_rate()
201 mtk_pll_set_rate_regs(clk, pcw, postdiv); in mtk_apmixedsys_set_rate()
210 u32 postdiv; in mtk_apmixedsys_get_rate() local
215 postdiv = 1 << postdiv; in mtk_apmixedsys_get_rate()
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| /u-boot/arch/mips/mach-ath79/qca956x/ |
| A D | clk.c | 314 u32 out_div, ref_div, postdiv, nint, hfrac, lfrac, clk_ctrl; in get_clocks() local
370 postdiv = (clk_ctrl >> QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) & in get_clocks()
376 cpu_rate = ddr_pll / (postdiv + 1); in get_clocks()
378 cpu_rate = cpu_pll / (postdiv + 1); in get_clocks()
380 postdiv = (clk_ctrl >> QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT) & in get_clocks()
386 ddr_rate = cpu_pll / (postdiv + 1); in get_clocks()
388 ddr_rate = ddr_pll / (postdiv + 1); in get_clocks()
390 postdiv = (clk_ctrl >> QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT) & in get_clocks()
396 ahb_rate = ddr_pll / (postdiv + 1); in get_clocks()
398 ahb_rate = cpu_pll / (postdiv + 1); in get_clocks()
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| /u-boot/drivers/clk/imx/ |
| A D | clk-composite-8m.c | 60 int *prediv, int *postdiv) in imx8m_clk_composite_compute_dividers() argument
67 *postdiv = 1; in imx8m_clk_composite_compute_dividers()
75 *postdiv = div2; in imx8m_clk_composite_compute_dividers()
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| /u-boot/drivers/clk/renesas/ |
| A D | clk-rcar-gen3.c | 166 u32 value, mult, div, prediv, postdiv; in gen3_clk_get_rate64() local
305 postdiv = (value >> CPG_RPC_POSTDIV_OFFSET) & in gen3_clk_get_rate64()
307 rate /= postdiv + 1; in gen3_clk_get_rate64()
311 core->parent, prediv, postdiv, rate); in gen3_clk_get_rate64()
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| /u-boot/arch/arm/mach-davinci/include/mach/ |
| A D | pll_defs.h | 24 unsigned int postdiv; /* 0x128 */ member
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| A D | hardware.h | 210 dv_reg postdiv; member
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| /u-boot/arch/arm/mach-davinci/ |
| A D | da850_lowlevel.c | 95 ®->postdiv); in da850_pll_init()
98 ®->postdiv); in da850_pll_init()
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