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Searched refs:pr (Results 1 – 23 of 23) sorted by relevance

/u-boot/arch/x86/cpu/
A Dirq.c271 struct pirq_routing pr; in create_pirq_routing_table() local
273 pr.bdf = fdt_addr_to_cpu(cell[0]); in create_pirq_routing_table()
274 pr.pin = fdt_addr_to_cpu(cell[1]); in create_pirq_routing_table()
278 i, PCI_BUS(pr.bdf), PCI_DEV(pr.bdf), in create_pirq_routing_table()
279 PCI_FUNC(pr.bdf), 'A' + pr.pin - 1, in create_pirq_routing_table()
280 'A' + pr.pirq); in create_pirq_routing_table()
283 PCI_BUS(pr.bdf), PCI_DEV(pr.bdf)); in create_pirq_routing_table()
286 PCI_BUS(pr.bdf), PCI_DEV(pr.bdf)); in create_pirq_routing_table()
288 if (slot->irq[pr.pin - 1].link) { in create_pirq_routing_table()
307 fill_irq_info(priv, slot, PCI_BUS(pr.bdf), PCI_DEV(pr.bdf), in create_pirq_routing_table()
[all …]
/u-boot/arch/x86/lib/
A Dmpspec.c321 struct pirq_routing pr; in mptable_add_intsrc() local
325 pr.bdf = fdt_addr_to_cpu(cell[0]); in mptable_add_intsrc()
326 pr.pin = fdt_addr_to_cpu(cell[1]); in mptable_add_intsrc()
327 pr.pirq = fdt_addr_to_cpu(cell[2]); in mptable_add_intsrc()
328 bus = PCI_BUS(pr.bdf); in mptable_add_intsrc()
329 dev = PCI_DEV(pr.bdf); in mptable_add_intsrc()
330 func = PCI_FUNC(pr.bdf); in mptable_add_intsrc()
333 bus, dev, pr.pin)) { in mptable_add_intsrc()
335 bus, dev, 'A' + pr.pin - 1); in mptable_add_intsrc()
340 dstirq = mp_determine_pci_dstirq(bus, dev, func, pr.pirq); in mptable_add_intsrc()
[all …]
/u-boot/drivers/pinctrl/meson/
A Dpinctrl-meson.h113 #define BANK_DS(n, f, l, per, peb, pr, pb, dr, db, or, ob, ir, ib, \ argument
121 [REG_PULL] = {pr, pb}, \
129 #define BANK(n, f, l, per, peb, pr, pb, dr, db, or, ob, ir, ib) \ argument
130 BANK_DS(n, f, l, per, peb, pr, pb, dr, db, or, ob, ir, ib, 0, 0)
/u-boot/arch/sh/lib/
A Dudivsi3.S27 sts.l pr,@-r15
44 lds.l @r15+,pr
63 lds.l @r15+,pr
A Dudivsi3_i4i-Os.S27 sts pr,r1
105 sts pr,r1
117 sts pr,r2
A Dstart.S21 1: sts pr, r5
A Dmovmem.S27 sts.l pr,@-r15
52 lds.l @r15+,pr
/u-boot/arch/arm/mach-lpc32xx/
A Dtimer.c32 writel(0, &timer->pr); in lpc32xx_timer_reset()
38 writel((get_periph_clk_rate() / freq) - 1, &timer->pr); in lpc32xx_timer_reset()
/u-boot/drivers/misc/
A Dfsl_ifc.c372 if (regs[i].pr && (regs[i].pr & CSPR_V)) { in init_early_memctl_regs()
376 ((regs[0].pr & CSPR_MSEL) == CSPR_MSEL_NOR))) { in init_early_memctl_regs()
388 set_ifc_cspr(i, regs[i].pr); in init_early_memctl_regs()
/u-boot/arch/arm/include/asm/arch-lpc32xx/
A Dtimer.h16 u32 pr; /* Prescale Register */ member
/u-boot/arch/sh/include/asm/
A Dptrace.h55 unsigned long pr; member
/u-boot/drivers/spi/
A Dich.h34 uint32_t pr[5]; /* 0x74 */ member
225 uint32_t *pr; /* only for ich9 */ member
A Dich.c821 ctlr->pr = &ich9_spi->pr[0]; in ich_init_controller()
/u-boot/drivers/pwm/
A Dpwm-imx.c43 writel(period_cycles, &pwm->pr); in pwm_config_internal()
/u-boot/board/ronetix/pm9263/
A Dpm9263.c194 writel(AT91_MATRIX_PRA_M5(3), &matrix->pr[5].a); in pm9263_lcd_hw_psram_init()
/u-boot/arch/arm/mach-at91/include/mach/
A Dat91_matrix.h61 at91_priority_t pr[AT91_MATRIX_SLAVES]; member
/u-boot/arch/arm/mach-sunxi/
A Ddram_sun9i.c698 clrsetbits_le32(&mctl_phy->zq[0].pr, 0xff, in mctl_channel_init()
700 clrsetbits_le32(&mctl_phy->zq[1].pr, 0xff, in mctl_channel_init()
702 clrsetbits_le32(&mctl_phy->zq[2].pr, 0xff, in mctl_channel_init()
/u-boot/arch/arm/include/asm/arch-sunxi/
A Ddram_sun9i.h141 u32 pr; /* impedance control data register */ member
/u-boot/arch/arm/include/asm/arch-mx25/
A Dimx-regs.h259 u32 pr; /* Period Register */ member
/u-boot/arch/arm/include/asm/arch-mx5/
A Dimx-regs.h520 u32 pr; member
/u-boot/include/
A Dfsl_ifc.h1039 u32 pr; member
/u-boot/arch/arm/include/asm/arch-mx6/
A Dimx-regs.h961 u32 pr; member
/u-boot/board/freescale/m54455evb/
A DREADME345 Linux version 2.6.20-gfe5136d6-dirty (mattw@kea) (gcc version 4.2.0 20070318 (pr

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