Searched refs:pregs (Results 1 – 4 of 4) sorted by relevance
| /u-boot/arch/arm/mach-mvebu/armada8k/ |
| A D | dram.c | 20 struct pt_regs pregs; in a8k_dram_scan_ap_sz() local
22 pregs.regs[0] = MV_SIP_DRAM_SIZE; in a8k_dram_scan_ap_sz()
23 pregs.regs[1] = SOC_REGS_PHY_BASE; in a8k_dram_scan_ap_sz()
24 smc_call(&pregs); in a8k_dram_scan_ap_sz()
26 return pregs.regs[0]; in a8k_dram_scan_ap_sz()
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| /u-boot/arch/mips/mach-ath79/ |
| A D | reset.c | 118 void __iomem *pregs = map_physmem(AR71XX_PLL_BASE, AR71XX_PLL_SIZE, in eth_init_ar933x() local
132 clrsetbits_be32(pregs + AR933X_PLL_SWITCH_CLOCK_CONTROL_REG, in eth_init_ar933x()
153 void __iomem *pregs = map_physmem(AR71XX_PLL_BASE, AR71XX_PLL_SIZE, in eth_init_ar934x() local
164 writel(0x570, pregs + AR934X_PLL_SWITCH_CLOCK_CONTROL_REG); in eth_init_ar934x()
166 writel(0x271, pregs + AR934X_PLL_SWITCH_CLOCK_CONTROL_REG); in eth_init_ar934x()
210 writel(BIT(2) | BIT(0), pregs + QCA956X_PLL_ETH_SGMII_SERDES_REG); in qca956x_sgmii_cal()
249 writel(BIT(2) | BIT(0), pregs + QCA956X_PLL_ETH_SGMII_SERDES_REG); in qca956x_sgmii_cal()
410 writel(0x45500, pregs + QCA956X_PLL_SWITCH_CLK_CTRL_REG); in eth_init_qca956x()
412 writel(0xc5200, pregs + QCA956X_PLL_SWITCH_CLK_CTRL_REG); in eth_init_qca956x()
420 pregs + QCA956X_PLL_ETH_XMII_CTRL_REG); in eth_init_qca956x()
[all …]
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| /u-boot/drivers/phy/marvell/ |
| A D | comphy_cp110.c | 249 struct pt_regs pregs = {0}; in comphy_smc() local
251 pregs.regs[0] = function_id; in comphy_smc()
252 pregs.regs[1] = (unsigned long)comphy_base_addr; in comphy_smc()
253 pregs.regs[2] = lane; in comphy_smc()
254 pregs.regs[3] = mode; in comphy_smc()
256 smc_call(&pregs); in comphy_smc()
263 return pregs.regs[0] ? 0 : 1; in comphy_smc()
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| /u-boot/include/ |
| A D | fm_eth.h | 72 #define FM_ETH_INFO_INITIALIZER(idx, pregs) \ argument
74 .phy_regs = (void *)pregs, \
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