Home
last modified time | relevance | path

Searched refs:ps (Results 1 – 25 of 105) sorted by relevance

12345

/u-boot/arch/x86/cpu/broadwell/
A Dpower_state.c24 if (ps->pm1_sts & WAK_STS) { in prev_sleep_state()
47 debug("PM1_EN: %04x\n", ps->pm1_en); in dump_power_state()
49 debug("TCO_STS: %04x %04x\n", ps->tco1_sts, ps->tco2_sts); in dump_power_state()
52 ps->gpe0_sts[0], ps->gpe0_sts[1], in dump_power_state()
53 ps->gpe0_sts[2], ps->gpe0_sts[3]); in dump_power_state()
55 ps->gpe0_en[0], ps->gpe0_en[1], in dump_power_state()
56 ps->gpe0_en[2], ps->gpe0_en[3]); in dump_power_state()
59 ps->gen_pmcon1, ps->gen_pmcon2, ps->gen_pmcon3); in dump_power_state()
62 ps->prev_sleep_state); in dump_power_state()
86 ps->prev_sleep_state = prev_sleep_state(ps); in power_state_get()
[all …]
/u-boot/doc/device-tree-bindings/net/
A Dmicrel-ksz90x1.txt27 0000 -840ps 0
28 0001 -720ps 120
29 0010 -600ps 240
30 0011 -480ps 360
31 0100 -360ps 480
34 0111 0ps 840
35 1000 120ps 960
63 step is 60ps.
90 0_1111 0ps 900
109 data pads, and the rxdv-skew-ps, txen-skew-ps control pads.
[all …]
/u-boot/arch/arm/dts/
A Dsocfpga_cyclone5_de0_nano_soc.dts48 txd0-skew-ps = <0>; /* -420ps */
49 txd1-skew-ps = <0>; /* -420ps */
50 txd2-skew-ps = <0>; /* -420ps */
51 txd3-skew-ps = <0>; /* -420ps */
52 rxd0-skew-ps = <420>; /* 0ps */
53 rxd1-skew-ps = <420>; /* 0ps */
54 rxd2-skew-ps = <420>; /* 0ps */
55 rxd3-skew-ps = <420>; /* 0ps */
56 txen-skew-ps = <0>; /* -420ps */
57 txc-skew-ps = <1860>; /* 960ps */
[all …]
A Dimx6dl-mba6.dtsi6 rxdv-skew-ps = <180>;
7 txen-skew-ps = <0>;
8 rxd3-skew-ps = <180>;
9 rxd2-skew-ps = <180>;
10 rxd1-skew-ps = <180>;
11 rxd0-skew-ps = <180>;
12 txd3-skew-ps = <120>;
13 txd2-skew-ps = <0>;
14 txd1-skew-ps = <300>;
15 txd0-skew-ps = <120>;
[all …]
A Dimx6q-mba6.dtsi6 rxdv-skew-ps = <180>;
7 txen-skew-ps = <120>;
8 rxd3-skew-ps = <180>;
9 rxd2-skew-ps = <180>;
10 rxd1-skew-ps = <180>;
11 rxd0-skew-ps = <180>;
12 txd3-skew-ps = <120>;
13 txd2-skew-ps = <0>;
14 txd1-skew-ps = <180>;
15 txd0-skew-ps = <360>;
[all …]
A Dsocfpga_stratix10_socdk.dts68 txd0-skew-ps = <0>; /* -420ps */
69 txd1-skew-ps = <0>; /* -420ps */
70 txd2-skew-ps = <0>; /* -420ps */
71 txd3-skew-ps = <0>; /* -420ps */
72 rxd0-skew-ps = <420>; /* 0ps */
73 rxd1-skew-ps = <420>; /* 0ps */
74 rxd2-skew-ps = <420>; /* 0ps */
75 rxd3-skew-ps = <420>; /* 0ps */
76 txen-skew-ps = <0>; /* -420ps */
77 txc-skew-ps = <900>; /* 0ps */
[all …]
A Dsocfpga_agilex_socdk.dts72 txd0-skew-ps = <0>; /* -420ps */
73 txd1-skew-ps = <0>; /* -420ps */
74 txd2-skew-ps = <0>; /* -420ps */
75 txd3-skew-ps = <0>; /* -420ps */
76 rxd0-skew-ps = <420>; /* 0ps */
77 rxd1-skew-ps = <420>; /* 0ps */
78 rxd2-skew-ps = <420>; /* 0ps */
79 rxd3-skew-ps = <420>; /* 0ps */
80 txen-skew-ps = <0>; /* -420ps */
81 txc-skew-ps = <900>; /* 0ps */
[all …]
A Dsocfpga_arria10_socdk.dtsi81 txd0-skew-ps = <0>; /* -420ps */
82 txd1-skew-ps = <0>; /* -420ps */
83 txd2-skew-ps = <0>; /* -420ps */
84 txd3-skew-ps = <0>; /* -420ps */
85 rxd0-skew-ps = <420>; /* 0ps */
86 rxd1-skew-ps = <420>; /* 0ps */
87 rxd2-skew-ps = <420>; /* 0ps */
88 rxd3-skew-ps = <420>; /* 0ps */
89 txen-skew-ps = <0>; /* -420ps */
90 txc-skew-ps = <1860>; /* 960ps */
[all …]
A Dsama5d3xcm.dtsi47 txen-skew-ps = <480>;
48 txc-skew-ps = <1800>;
49 rxdv-skew-ps = <240>;
50 rxc-skew-ps = <1800>;
51 rxd0-skew-ps = <240>;
52 rxd1-skew-ps = <240>;
53 rxd2-skew-ps = <240>;
54 rxd3-skew-ps = <240>;
61 txen-skew-ps = <480>;
62 txc-skew-ps = <1800>;
[all …]
A Dsama5d3xcm_cmp.dtsi46 txen-skew-ps = <480>;
47 txc-skew-ps = <1800>;
48 rxdv-skew-ps = <240>;
49 rxc-skew-ps = <1800>;
50 rxd0-skew-ps = <240>;
51 rxd1-skew-ps = <240>;
52 rxd2-skew-ps = <240>;
53 rxd3-skew-ps = <240>;
60 txen-skew-ps = <480>;
61 txc-skew-ps = <1800>;
[all …]
A Dsocfpga_cyclone5_de10_nano.dts36 rxd0-skew-ps = <420>;
37 rxd1-skew-ps = <420>;
38 rxd2-skew-ps = <420>;
39 rxd3-skew-ps = <420>;
40 txen-skew-ps = <0>;
41 txc-skew-ps = <1860>;
42 rxdv-skew-ps = <420>;
43 rxc-skew-ps = <1680>;
A Dsocfpga_cyclone5_de1_soc.dts34 rxd0-skew-ps = <420>;
35 rxd1-skew-ps = <420>;
36 rxd2-skew-ps = <420>;
37 rxd3-skew-ps = <420>;
38 txen-skew-ps = <0>;
39 txc-skew-ps = <1860>;
40 rxdv-skew-ps = <420>;
41 rxc-skew-ps = <1680>;
A Dzynqmp-zcu1275-revB.dts51 rxc-skew-ps = <1800>; /* Skew control of RX_CLK pad output */
53 txen-skew-ps = <900>; /* Skew control of TX_CTL pad input */
54 rxdv-skew-ps = <0>; /* Skew control of RX_CTL pad output */
55 rxd0-skew-ps = <0>; /* Skew control of RXD0 pad output */
56 rxd1-skew-ps = <0>; /* Skew control of RXD1 pad output */
57 rxd2-skew-ps = <0>; /* Skew control of RXD2 pad output */
58 rxd3-skew-ps = <0>; /* Skew control of RXD3 pad output */
59 txd0-skew-ps = <900>; /* Skew control of TXD0 pad input */
60 txd1-skew-ps = <900>; /* Skew control of TXD1 pad input */
61 txd2-skew-ps = <900>; /* Skew control of TXD2 pad input */
[all …]
A Dsocfpga_cyclone5_is1.dts41 rxd0-skew-ps = <0>;
42 rxd1-skew-ps = <0>;
43 rxd2-skew-ps = <0>;
44 rxd3-skew-ps = <0>;
45 txen-skew-ps = <0>;
46 txc-skew-ps = <1560>;
47 rxdv-skew-ps = <0>;
48 rxc-skew-ps = <1200>;
A Darmada-xp-crs328-4c-20s-4s.dtsi55 devbus,turn-off-ps = <60000>;
56 devbus,badr-skew-ps = <0>;
57 devbus,acc-first-ps = <124000>;
58 devbus,acc-next-ps = <248000>;
59 devbus,rd-setup-ps = <0>;
60 devbus,rd-hold-ps = <0>;
64 devbus,wr-high-ps = <60000>;
65 devbus,wr-low-ps = <60000>;
66 devbus,ale-wr-ps = <60000>;
A Darmada-xp-crs305-1g-4s.dtsi55 devbus,turn-off-ps = <60000>;
56 devbus,badr-skew-ps = <0>;
57 devbus,acc-first-ps = <124000>;
58 devbus,acc-next-ps = <248000>;
59 devbus,rd-setup-ps = <0>;
60 devbus,rd-hold-ps = <0>;
64 devbus,wr-high-ps = <60000>;
65 devbus,wr-low-ps = <60000>;
66 devbus,ale-wr-ps = <60000>;
A Darmada-xp-crs326-24g-2s.dtsi55 devbus,turn-off-ps = <60000>;
56 devbus,badr-skew-ps = <0>;
57 devbus,acc-first-ps = <124000>;
58 devbus,acc-next-ps = <248000>;
59 devbus,rd-setup-ps = <0>;
60 devbus,rd-hold-ps = <0>;
64 devbus,wr-high-ps = <60000>;
65 devbus,wr-low-ps = <60000>;
66 devbus,ale-wr-ps = <60000>;
A Darmada-xp-db-xc3-24g4xg.dts54 devbus,turn-off-ps = <60000>;
55 devbus,badr-skew-ps = <0>;
56 devbus,acc-first-ps = <124000>;
57 devbus,acc-next-ps = <248000>;
58 devbus,rd-setup-ps = <0>;
59 devbus,rd-hold-ps = <0>;
63 devbus,wr-high-ps = <60000>;
64 devbus,wr-low-ps = <60000>;
65 devbus,ale-wr-ps = <60000>;
A Dsocfpga_cyclone5_vining_fpga.dts88 rxd0-skew-ps = <0>;
89 rxd1-skew-ps = <0>;
90 rxd2-skew-ps = <0>;
91 rxd3-skew-ps = <0>;
92 txd0-skew-ps = <0>;
93 txd1-skew-ps = <0>;
94 txd2-skew-ps = <0>;
95 txd3-skew-ps = <0>;
96 txen-skew-ps = <0>;
97 txc-skew-ps = <1860>;
[all …]
A Dsocfpga_arria5_socdk.dts65 rxd0-skew-ps = <0>;
66 rxd1-skew-ps = <0>;
67 rxd2-skew-ps = <0>;
68 rxd3-skew-ps = <0>;
69 txen-skew-ps = <0>;
70 txc-skew-ps = <1560>;
71 rxdv-skew-ps = <0>;
72 rxc-skew-ps = <1200>;
A Dsocfpga_cyclone5_socdk.dts69 rxd0-skew-ps = <0>;
70 rxd1-skew-ps = <0>;
71 rxd2-skew-ps = <0>;
72 rxd3-skew-ps = <0>;
73 txen-skew-ps = <0>;
74 txc-skew-ps = <1560>;
75 rxdv-skew-ps = <0>;
76 rxc-skew-ps = <1200>;
A Dsocfpga_cyclone5_sockit.dts126 rxd0-skew-ps = <0>;
127 rxd1-skew-ps = <0>;
128 rxd2-skew-ps = <0>;
129 rxd3-skew-ps = <0>;
130 txen-skew-ps = <0>;
131 txc-skew-ps = <1560>;
132 rxdv-skew-ps = <0>;
133 rxc-skew-ps = <1200>;
A Dzynqmp-zcu1285-revA.dts232 rxc-skew-ps = <1800>; /* Skew control of RX_CLK pad output */
234 txen-skew-ps = <900>; /* Skew control of TX_CTL pad input */
235 rxdv-skew-ps = <0>; /* Skew control of RX_CTL pad output */
236 rxd0-skew-ps = <0>; /* Skew control of RXD0 pad output */
237 rxd1-skew-ps = <0>; /* Skew control of RXD1 pad output */
238 rxd2-skew-ps = <0>; /* Skew control of RXD2 pad output */
239 rxd3-skew-ps = <0>; /* Skew control of RXD3 pad output */
240 txd0-skew-ps = <900>; /* Skew control of TXD0 pad input */
241 txd1-skew-ps = <900>; /* Skew control of TXD1 pad input */
242 txd2-skew-ps = <900>; /* Skew control of TXD2 pad input */
[all …]
/u-boot/drivers/spi/
A Dpl022_spi.c97 ps->freq = plat->freq; in pl022_spi_probe()
100 if (!pl022_is_supported(ps)) in pl022_spi_probe()
114 readw(ps->base + SSP_DR); in flush()
125 reg = readw(ps->base + SSP_CR1); in pl022_spi_claim_bus()
127 writew(reg, ps->base + SSP_CR1); in pl022_spi_claim_bus()
129 flush(ps); in pl022_spi_claim_bus()
140 flush(ps); in pl022_spi_release_bus()
143 reg = readw(ps->base + SSP_CR1); in pl022_spi_release_bus()
145 writew(reg, ps->base + SSP_CR1); in pl022_spi_release_bus()
218 u32 rate = ps->freq; in pl022_spi_set_speed()
[all …]
/u-boot/arch/arm/mach-sunxi/
A Ddram_sun9i.c86 u32 ps; member
401 PS2CYCLES_ROUNDUP(para->tZQCS.ps)); in mctl_channel_init()
896 .tRTP = { .ck = 4, .ps = 7500 }, in sunxi_dram_init()
897 .tWTR = { .ck = 4, .ps = 7500 }, in sunxi_dram_init()
900 .tMOD = { .ck = 12, .ps = 15000 }, in sunxi_dram_init()
902 .tRRD = { .ck = 4, .ps = 7500 }, in sunxi_dram_init()
914 .tXS = { .ck = 5, .ps = 10000 }, in sunxi_dram_init()
916 .tCKSRE = { .ck = 5, .ps = 10000 }, in sunxi_dram_init()
917 .tCKSRX = { .ck = 5, .ps = 10000 }, in sunxi_dram_init()
920 .tXP = { .ck = 3, .ps = 6000 }, in sunxi_dram_init()
[all …]

Completed in 22 milliseconds

12345