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Searched refs:ptr0 (Results 1 – 16 of 16) sorted by relevance

/u-boot/board/ti/ks2_evm/
A Dddr3_k2g.c20 .ptr0 = 0x42C21590ul,
60 .ptr0 = 0x42C21590ul,
121 .ptr0 = 0x42C21590ul,
A Dddr3_cfg.c18 .ptr0 = 0x42C21590ul,
/u-boot/arch/arm/mach-keystone/include/mach/
A Dddr3.h18 unsigned int ptr0; member
/u-boot/board/imgtec/ci20/
A Dci20.c297 .ptr0 = 0x002000d4,
341 .ptr0 = 0x002000d4,
/u-boot/arch/arm/include/asm/arch-sunxi/
A Ddram_sun8i_a33.h83 u32 ptr0; /* 0x44 */ member
A Ddram_sun8i_a83t.h83 u32 ptr0; /* 0x44 */ member
A Ddram_sun8i_a23.h170 u32 ptr0; /* 0x1c */ member
A Ddram_sun6i.h167 u32 ptr0; /* 0x18 */ member
/u-boot/drivers/ram/stm32mp1/
A Dstm32mp1_ddr.h131 u32 ptr0; member
A Dstm32mp1_ddr_regs.h148 u32 ptr0; /* 0x18 R/W PHY Timing 0*/ member
A Dstm32mp1_ddr.c169 DDRPHY_REG_TIMING(ptr0),
/u-boot/arch/arm/mach-keystone/
A Dddr3_spd.c25 debug_ddr_cfg("ptr0 0x%08X\n", ptr->ptr0); in dump_phy_config()
308 spd_cb->phy_cfg.ptr0 = ((spd->t_pllpd & 0x7ff) << 21) | in init_ddr3param()
A Dddr3.c42 __raw_writel(phy_cfg->ptr0, base + KS2_DDRPHY_PTR0_OFFSET); in ddr3_init_ddrphy()
/u-boot/arch/mips/mach-jz47xx/jz4780/
A Dsdram.c83 writel(ddr_config->ptr0, ddr_phy_regs + DDRP_PTR0); in ddr_phy_init()
/u-boot/arch/mips/mach-jz47xx/include/mach/
A Djz4780_dram.h441 u32 ptr0; /* PHY Timing Register 0 */ member
/u-boot/arch/arm/mach-sunxi/
A Ddram_sun6i.c130 &mctl_phy->ptr0); in mctl_channel_init()

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