Searched refs:ptr0 (Results 1 – 16 of 16) sorted by relevance
/u-boot/board/ti/ks2_evm/ |
A D | ddr3_k2g.c | 20 .ptr0 = 0x42C21590ul, 60 .ptr0 = 0x42C21590ul, 121 .ptr0 = 0x42C21590ul,
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A D | ddr3_cfg.c | 18 .ptr0 = 0x42C21590ul,
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/u-boot/arch/arm/mach-keystone/include/mach/ |
A D | ddr3.h | 18 unsigned int ptr0; member
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/u-boot/board/imgtec/ci20/ |
A D | ci20.c | 297 .ptr0 = 0x002000d4, 341 .ptr0 = 0x002000d4,
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/u-boot/arch/arm/include/asm/arch-sunxi/ |
A D | dram_sun8i_a33.h | 83 u32 ptr0; /* 0x44 */ member
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A D | dram_sun8i_a83t.h | 83 u32 ptr0; /* 0x44 */ member
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A D | dram_sun8i_a23.h | 170 u32 ptr0; /* 0x1c */ member
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A D | dram_sun6i.h | 167 u32 ptr0; /* 0x18 */ member
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/u-boot/drivers/ram/stm32mp1/ |
A D | stm32mp1_ddr.h | 131 u32 ptr0; member
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A D | stm32mp1_ddr_regs.h | 148 u32 ptr0; /* 0x18 R/W PHY Timing 0*/ member
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A D | stm32mp1_ddr.c | 169 DDRPHY_REG_TIMING(ptr0),
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/u-boot/arch/arm/mach-keystone/ |
A D | ddr3_spd.c | 25 debug_ddr_cfg("ptr0 0x%08X\n", ptr->ptr0); in dump_phy_config() 308 spd_cb->phy_cfg.ptr0 = ((spd->t_pllpd & 0x7ff) << 21) | in init_ddr3param()
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A D | ddr3.c | 42 __raw_writel(phy_cfg->ptr0, base + KS2_DDRPHY_PTR0_OFFSET); in ddr3_init_ddrphy()
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/u-boot/arch/mips/mach-jz47xx/jz4780/ |
A D | sdram.c | 83 writel(ddr_config->ptr0, ddr_phy_regs + DDRP_PTR0); in ddr_phy_init()
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/u-boot/arch/mips/mach-jz47xx/include/mach/ |
A D | jz4780_dram.h | 441 u32 ptr0; /* PHY Timing Register 0 */ member
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/u-boot/arch/arm/mach-sunxi/ |
A D | dram_sun6i.c | 130 &mctl_phy->ptr0); in mctl_channel_init()
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