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Searched refs:pup (Results 1 – 10 of 10) sorted by relevance

/u-boot/drivers/ddr/marvell/a38x/
A Dddr3_training_pbs.c86 for (pup = 0; pup < octets_per_if_num; pup++) { in ddr3_tip_pbs()
99 for (pup = 0; pup < octets_per_if_num; pup++) { in ddr3_tip_pbs()
175 for (pup = 0; pup < octets_per_if_num; pup++) { in ddr3_tip_pbs()
334 for (pup = 0; pup < octets_per_if_num; pup++) { in ddr3_tip_pbs()
349 for (pup = 0; pup < octets_per_if_num; pup++) { in ddr3_tip_pbs()
372 for (pup = 0; pup < octets_per_if_num; pup++) { in ddr3_tip_pbs()
399 for (pup = 0; pup < octets_per_if_num; pup++) { in ddr3_tip_pbs()
460 for (pup = 0; pup < octets_per_if_num; pup++) { in ddr3_tip_pbs()
477 for (pup = 0; pup < octets_per_if_num; pup++) { in ddr3_tip_pbs()
626 for (pup = 0; pup < octets_per_if_num; pup++) { in ddr3_tip_pbs()
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A Dddr3_training_hw_algo.c184 for (pup = 0; in ddr3_tip_vref()
185 pup < octets_per_if_num; pup++) { in ddr3_tip_vref()
212 if_id, pup, in ddr3_tip_vref()
261 for (pup = 0; in ddr3_tip_vref()
262 pup < octets_per_if_num; pup++) { in ddr3_tip_vref()
275 for (pup = 0; in ddr3_tip_vref()
276 pup < octets_per_if_num; pup++) { in ddr3_tip_vref()
366 [pup] in ddr3_tip_vref()
406 [pup] in ddr3_tip_vref()
603 for (pup = 0; in ddr3_tip_vref()
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A Dddr3_debug.c980 for (pup = start_pup; pup <= end_pup; pup++) { in ddr3_tip_run_sweep_test()
997 for (pup = start_pup; pup <= end_pup; pup++) { in ddr3_tip_run_sweep_test()
1027 pup, in ddr3_tip_run_sweep_test()
1045 for (pup = start_pup; pup <= end_pup; pup++) { in ddr3_tip_run_sweep_test()
1064 for (pup = start_pup; pup <= end_pup; pup++) { in ddr3_tip_run_sweep_test()
1120 for (pup = start_pup; pup <= end_pup; pup++) in ddr3_tip_run_leveling_sweep_test()
1142 for (pup = start_pup; pup <= end_pup; pup++) { in ddr3_tip_run_leveling_sweep_test()
1170 pup, in ddr3_tip_run_leveling_sweep_test()
1230 pup, in ddr3_tip_run_leveling_sweep_test()
1245 for (pup = start_pup; pup <= end_pup; pup++) { in ddr3_tip_run_leveling_sweep_test()
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/u-boot/drivers/ddr/marvell/axp/
A Dddr3_dqs.c327 for (pup = 0; pup < max_pup; pup++) { in ddr3_find_adll_limits()
343 for (pup = 0; pup < max_pup; pup++) in ddr3_find_adll_limits()
346 for (pup = 0; pup < max_pup; pup++) { in ddr3_find_adll_limits()
368 for (pup = 0; pup < max_pup; pup++) in ddr3_find_adll_limits()
378 for (pup = 0; pup < max_pup; pup++) { in ddr3_find_adll_limits()
392 for (pup = 0; pup < max_pup; pup++) { in ddr3_find_adll_limits()
434 for (pup = 0; pup < max_pup; pup++) { in ddr3_find_adll_limits()
773 for (pup = 0; pup < max_pup; pup++) { in ddr3_find_adll_limits()
793 for (pup = 0; pup < max_pup; pup++) { in ddr3_find_adll_limits()
972 for (pup = 0; pup < max_pup; pup++) in ddr3_special_pattern_i_search()
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A Dddr3_pbs.c125 for (pup = 0; pup < pups; pup++) { in ddr3_pbs_tx()
294 for (pup = 0; pup < max_pup; pup++) { in ddr3_pbs_tx()
323 for (pup = 0; pup < max_pup; pup++) { in ddr3_pbs_tx()
338 for (pup = 0; pup < max_pup; pup++) { in ddr3_pbs_tx()
345 for (pup = 0; pup < max_pup; pup++) { in ddr3_pbs_tx()
371 for (pup = 0; pup < max_pup; pup++) { in ddr3_pbs_tx()
452 for (pup = 0; pup < cur_max_pup; pup++) in ddr3_tx_shift_dqs_adll_step_before_fail()
505 for (pup = 0; pup < cur_max_pup; pup++) in ddr3_tx_shift_dqs_adll_step_before_fail()
568 for (pup = 0; pup < pups; pup++) { in ddr3_pbs_rx()
854 for (pup = 0; pup < max_pup; pup++) { in ddr3_pbs_rx()
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A Dddr3_write_leveling.c294 for (pup = 0; pup < max_pup_num; pup++) { in ddr3_wl_supplement()
397 pup = (ecc) ? max_pup_num : pup; in ddr3_wl_supplement()
410 for (pup = 0; pup < dram_info->num_of_std_pups; pup++) in ddr3_wl_supplement()
434 for (pup = 0; pup < dram_info->num_of_total_pups; pup++) { in ddr3_wl_supplement()
490 for (pup = 0; pup <= dram_info->num_of_total_pups; pup++) { in ddr3_write_leveling_hw_reg_dimm()
775 for (pup = 0; pup < max_pup_num; pup++) { in ddr3_write_leveling_sw()
906 for (pup = 0; pup <= dram_info->num_of_total_pups; pup++) { in ddr3_write_leveling_sw_reg_dimm()
1105 for (pup = 0; pup <= dram_info->num_of_total_pups; pup++) { in ddr3_write_leveling_sw_reg_dimm()
1264 for (pup = 0; pup < (max_pup_num); pup++) { in ddr3_write_leveling_single_cs()
1303 for (pup = 0; pup < (max_pup_num); pup++) { in ddr3_write_leveling_single_cs()
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A Dddr3_read_leveling.c422 pup++) in ddr3_read_leveling_single_cs_rl_mode()
467 for (pup = 0; pup < (dram_info->num_of_std_pups * (1 - ecc) + ecc); pup++) { in ddr3_read_leveling_single_cs_rl_mode()
577 for (pup = 0; pup < (dram_info->num_of_std_pups * (1 - ecc) + ecc); pup++) { in ddr3_read_leveling_single_cs_rl_mode()
605 for (pup = 0; pup < (dram_info->num_of_std_pups * (1 - ecc) + ecc); pup++) { in ddr3_read_leveling_single_cs_rl_mode()
678 for (pup = 0; pup < in ddr3_read_leveling_single_cs_rl_mode()
689 for (pup = 0; pup < (dram_info->num_of_std_pups); pup++) { in ddr3_read_leveling_single_cs_rl_mode()
731 for (pup = 0; pup < dram_info->num_of_total_pups; pup++) { in ddr3_read_leveling_single_cs_rl_mode()
776 pup++) in ddr3_read_leveling_single_cs_window_mode()
820 for (pup = 0; pup < (dram_info->num_of_std_pups * in ddr3_read_leveling_single_cs_window_mode()
1092 for (pup = 0; pup < (dram_info->num_of_std_pups); pup++) { in ddr3_read_leveling_single_cs_window_mode()
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A Dddr3_sdram.c107 *pup |= (1 << (uk + (PUP_NUM_32BIT * in compare_pattern_v1()
143 *pup |= (1 << (uk % PUP_NUM_16BIT)); in compare_pattern_v2()
225 u32 pup = 0; in ddr3_sdram_dm_compare() local
258 *new_locked_pup |= pup; in ddr3_sdram_dm_compare()
291 u32 ui, dq, pup; in ddr3_sdram_pbs_compare() local
340 for (pup = 0; pup < PUP_NUM_32BIT; pup++) { in ddr3_sdram_pbs_compare()
341 val = CMP_BYTE_SHIFT * pup; in ddr3_sdram_pbs_compare()
349 tmp_pup = (pup + PUP_NUM_32BIT * in ddr3_sdram_pbs_compare()
352 tmp_pup = (pup % PUP_NUM_16BIT); in ddr3_sdram_pbs_compare()
405 for (pup = 0; pup < max_pup; pup++) { in ddr3_sdram_pbs_compare()
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A Dddr3_hw_training.c553 if (pup == PUP_BC) in ddr3_write_pup_reg()
577 if (pup == PUP_BC) in ddr3_write_pup_reg()
699 u32 val, pup, tmp_cs, cs, i, dq; in ddr3_save_training() local
720 for (pup = 0; pup < dram_info->num_of_total_pups; in ddr3_save_training()
721 pup++) { in ddr3_save_training()
724 pup = ECC_PUP; in ddr3_save_training()
732 mode_config[i], CS0, pup); in ddr3_save_training()
745 pup); in ddr3_save_training()
754 mode_config[i], cs, pup); in ddr3_save_training()
1050 u32 pup, reg, phase; in ddr3_get_min_max_rl_phase() local
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A Dddr3_hw_training.h326 void ddr3_write_pup_reg(u32 mode, u32 cs, u32 pup, u32 phase, u32 delay);
327 u32 ddr3_read_pup_reg(u32 mode, u32 cs, u32 pup);

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