Searched refs:pwr_mng_ctrl_reg (Results 1 – 2 of 2) sorted by relevance
158 u32 pwr_mng_ctrl_reg; in board_init() local169 pwr_mng_ctrl_reg = reg_read(POWER_MNG_CTRL_REG); in board_init()170 pwr_mng_ctrl_reg &= ~(BIT(0)); /* Audio */ in board_init()171 pwr_mng_ctrl_reg &= ~(BIT(1) | BIT(2)); /* GE3, GE2 */ in board_init()172 pwr_mng_ctrl_reg &= ~(BIT(14) | BIT(15)); /* SATA0 link and core */ in board_init()173 pwr_mng_ctrl_reg &= ~(BIT(16)); /* LCD */ in board_init()174 pwr_mng_ctrl_reg &= ~(BIT(17)); /* SDIO */ in board_init()175 pwr_mng_ctrl_reg &= ~(BIT(19) | BIT(20)); /* USB1 and USB2 */ in board_init()176 pwr_mng_ctrl_reg &= ~(BIT(29) | BIT(30)); /* SATA1 link and core */ in board_init()177 reg_write(POWER_MNG_CTRL_REG, pwr_mng_ctrl_reg); in board_init()
158 u32 pwr_mng_ctrl_reg = reg_read(POWER_MNG_CTRL_REG); in do_syno_clk_gate() local171 state = pwr_mng_ctrl_reg & (1 << i) ? "ON" : "OFF"; in do_syno_clk_gate()192 pwr_mng_ctrl_reg |= (val << i); in do_syno_clk_gate()193 pwr_mng_ctrl_reg &= ~(!val << i); in do_syno_clk_gate()194 reg_write(POWER_MNG_CTRL_REG, pwr_mng_ctrl_reg); in do_syno_clk_gate()
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