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Searched refs:r5 (Results 1 – 25 of 85) sorted by relevance

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/u-boot/arch/powerpc/lib/
A Dppcstring.S24 mtctr r5
40 addi r5,r5,-1
78 add r5,r0,r5
85 6: andi. r5,r5,3
88 mtctr r5
114 andi. r5,r5,7
118 addi r5,r5,-4
136 subf r5,r0,r5
156 andi. r5,r5,7
160 subi r5,r5,4
[all …]
A Dppccache.S68 li r5,L1_CACHE_BYTES-1
69 andc r3,r3,r5
71 add r4,r4,r5
92 li r5,L1_CACHE_BYTES-1
93 andc r3,r3,r5
95 add r4,r4,r5
A D_ashldi3.S33 subfic r6,r5,32
34 slw r3,r3,r5 # MSW = count > 31 ? 0 : MSW << count
35 addi r7,r5,32 # could be xori, or addi with -32
39 slw r4,r4,r5 # LSW = LSW << count
A D_lshrdi3.S33 subfic r6,r5,32
34 srw r4,r4,r5 # LSW = count > 31 ? 0 : LSW >> count
35 addi r7,r5,32 # could be xori, or addi with -32
39 srw r3,r3,r5 # MSW = MSW >> count
/u-boot/arch/nios2/cpu/
A Dstart.S35 ori r5, r5, %lo(ICACHE_SIZE_MAX)
36 0: initi r5
37 sub r5, r5, r4
38 bgt r5, r0, 0b
64 ori r5, r5, %lo(DCACHE_SIZE_MAX)
78 ori r5, r5, %lo(_cur - _start)
82 ori r5, r5, %lo(_start) /* r5 <- linked _start */
92 addi r5, r5, 4
159 mov r4, r5
166 ori r5, r5, %lo(__bss_start)
[all …]
/u-boot/arch/sh/lib/
A Dudivsi3_i4i-Os.S36 shll16 r5
38 div1 r5,r4
40 div1 r5,r4
41 div1 r5,r4
43 div1 r5,r4
48 div1 r5,r4
50 div1 r5,r4
60 div1 r5,r4; div1 r5,r4; div1 r5,r4
61 div1 r5,r4; div1 r5,r4; rts; div1 r5,r4
93 cmp/pz r5
[all …]
A Dudivsi3.S15 div1 r5,r4
17 div1 r5,r4; div1 r5,r4; div1 r5,r4
18 div1 r5,r4; div1 r5,r4; div1 r5,r4; rts; div1 r5,r4
21 div1 r5,r4; rotcl r0
24 rts; div1 r5,r4
28 extu.w r5,r0
29 cmp/eq r5,r0
35 shll16 r5
37 div1 r5,r4
43 div1 r5,r4
[all …]
A Dudivsi3_i4i.S51 mov r5,r1
52 shll16 r5
54 div1 r5,r0
56 div1 r5,r0
57 div1 r5,r0
59 div1 r5,r0
73 mov r5,r0
99 shll8 r5
104 mov r5,r1
106 shll8 r5
[all …]
A Dmovmem.S42 add #64,r5
178 mov.l @r5+,r0
180 mov.l @r5+,r1
183 mov.l @r5+,r1
185 mov.l @r5+,r2
186 mov.l @r5+,r3
193 mov.l @r5+,r0
195 mov.l @r5+,r1
198 mov.l @r5+,r2
199 mov.l @r5+,r3
[all …]
A Dstart.S21 1: sts pr, r5
23 add #(_start-1b), r5
27 add r5, r0
37 2: mov.l @r5+, r1
45 mov.l ._bss_end, r5
50 cmp/hs r5, r4
/u-boot/arch/nds32/include/asm/
A Dmacro.h26 li $r5, \data
27 swi $r5, [$r4]
32 li $r5, \data
33 shi $r5, [$r4]
38 li $r5, \data
39 sbi $r5, [$r4]
49 lwi $r5, [$r4]
51 or $r5, $r5, $r6
52 swi $r5, [$r4]
57 lwi $r5, [$r4]
[all …]
/u-boot/arch/arc/lib/
A Dstart.S16 lr r5, [ARC_BCR_IC_BUILD]
17 breq r5, 0, 1f ; I$ doesn't exist
38 lr r5, [ARC_AUX_DC_CTRL]
39 bclr r5, r5, 6 ; Invalidate (discard w/o wback)
41 bclr r5, r5, 0 ; Enable (+Inv)
43 bset r5, r5, 0 ; Disable (+Inv)
45 sr r5, [ARC_AUX_DC_CTRL]
47 mov r5, 1
48 sr r5, [ARC_AUX_DC_IVDC]
54 lr r5, [ARC_BCR_SLC]
[all …]
/u-boot/arch/arm/mach-tegra/
A Dpsci.S42 bic r5, r5, #1 @ Secure mode
48 ldr r5, [r4]
49 orr r5, r5, #NS_RST_VEC_WR_DIS
50 str r5, [r4]
58 streq r7, [r5]
60 ldrne r7, [r5]
79 add r5, r4, lsl r0
80 str r5, [r6, r2]
98 str r5, [r6]
104 str r5, [r6, r2]
[all …]
/u-boot/arch/powerpc/cpu/mpc86xx/
A Dcache.S59 cmp 0,1,r3,r5
61 lwz r5,0(r3)
76 andc r3,r3,r5
78 add r4,r4,r5
177 andc r3, r3, r5
180 mtspr HID0, r5
194 li r5, 0
195 ori r5, r5, HID0_ICE
196 andc r3, r3, r5
237 mflr r5
[all …]
/u-boot/board/nokia/rx51/
A Dlowlevel_init.S71 mov r5, #0
72 str r5, [r3]
77 cmp r4, r5
87 mov r5, #0
101 subhi r5, r0, r1
102 sublo r5, r1, r0
111 addhi r0, r1, r5
112 sublo r0, r1, r5
115 cmp r5, r6
133 add r5, r5, r6
[all …]
/u-boot/arch/arm/include/asm/arch-mx7ulp/
A Dmx7ulp_plugin.S54 push {r5}
55 ldr r5, boot_data2
56 str r5, [r0]
57 ldr r5, image_len2
58 str r5, [r1]
59 ldr r5, second_ivt_offset
60 str r5, [r2]
62 pop {r5}
/u-boot/arch/nds32/cpu/n1213/ag101/
A Dlowlevel_init.S200 li $r5, 0x0
235 li $r5, AHBC_BSR6_A
236 lwi $r8, [$r5]
245 blt $r5, $r6, 1b
259 add $r10, $r10, $r5
268 lwi $r6, [$r5]
273 swi $r6, [$r5]
280 lwi $r5, [$r4]
282 and $r5, $r5, $r6
284 or $r5, $r5, $r6
[all …]
/u-boot/arch/microblaze/cpu/
A Dstart.S31 add r5, r0, r1
43 add r5, r0, r3
49 or r5, r0, r0
55 addik r5, r0, 0
69 cmp r6, r5, r4
73 addi r5, r5, 4 /* increment to next loc */
228 in16: lhu r3, r0, r5
249 sh r3, r0, r5
276 or r5, r0, r0
281 addi r5, r5, 4 /* Increment to next loc - relocate code */
[all …]
/u-boot/post/lib_powerpc/
A Dasm.S27 mr r4, r5
50 mr r4, r5
51 mr r5, r6
72 mr r3, r5
93 mr r3, r5
174 mr r4, r5
175 mr r5, r6
196 mr r4, r5
218 mr r4, r5
224 stw r5, 0(r4)
[all …]
/u-boot/arch/arm/include/asm/arch-mx7/
A Dmx7_plugin.S71 push {r5}
72 ldr r5, boot_data2
73 str r5, [r0]
74 ldr r5, image_len2
75 str r5, [r1]
76 ldr r5, second_ivt_offset
77 str r5, [r2]
79 pop {r5}
/u-boot/arch/arm/mach-omap2/omap3/
A Dlowlevel_init.S78 and r5, r5, #0x1 /* isolate core status */
83 ldr r5, pll_div_add1
89 str r2, [r5]
92 str r2, [r5]
95 str r2, [r5]
101 str r2, [r5]
104 str r2, [r5]
107 str r2, [r5]
109 ldr r2, [r5]
111 str r2, [r5]
[all …]
/u-boot/arch/arm/cpu/armv7/
A Dnonsec_virt.S48 mcr p15, 0, r5, c12, c0, 1
61 mrc p15, 0, r5, c1, c0, 1
62 orr r5, r5, #(1 << 1)
63 mcr p15, 0, r5, c1, c0, 1
68 mrc p15, 0, r5, c1, c0, 1
69 orr r5, r5, #(1 << 25)
70 mcr p15, 0, r5, c1, c0, 1
74 mrc p15, 0, r5, c1, c1, 0 @ read SCR
75 bic r5, r5, #0x4a @ clear IRQ, EA, nET bits
76 orr r5, r5, #0x31 @ enable NS, AW, FW bits
[all …]
/u-boot/arch/arm/mach-omap2/omap5/
A Dsec_entry_cpu1.S64 mov r5, #0x0
65 str r5, [r4]
79 push {r4, r5, lr}
89 ldr r5, =cpu1_entry
90 str r5, [r4] @ Setup CPU1 entry function
92 mov r5, #0x10
93 str r5, [r4] @ Tell ROM to exit while loop
98 ldr r5, [r4] @ Check if CPU1 is done
99 cmp r5, #0
104 pop {r4, r5, pc}
/u-boot/arch/arm/include/asm/arch-mx6/
A Dmx6_plugin.S115 push {r5}
116 ldr r5, boot_data2
117 str r5, [r0]
118 ldr r5, image_len2
119 str r5, [r1]
120 ldr r5, second_ivt_offset
121 str r5, [r2]
123 pop {r5}
/u-boot/arch/powerpc/cpu/mpc83xx/
A Dstart.S104 mfmsr r5
105 ori r5, r5, (MSR_IR | MSR_DR)
106 mtmsr r5
204 mtlr r5
715 lis r5, 2
828 sub r5, r5, r4
895 add r5,r3,r5
1144 1: srawi. r5, r5, 1 /* r5 = r5 >> 1 */
1165 ori r5, r5, (CONFIG_SYS_FLASH_BASE & 0xFFFF8000)@l
1166 or r5, r5, r4
[all …]

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