| /u-boot/arch/arm/mach-bcmstb/ |
| A D | lowlevel_init.S | 11 ldr r6, =bcmstb_boot_parameters
12 str r0, [r6, #0]
13 str r1, [r6, #4]
14 str r2, [r6, #8]
15 str r3, [r6, #12]
16 str sp, [r6, #16]
17 str lr, [r6, #20]
18 ldr r6, =prior_stage_fdt_address
19 str r2, [r6]
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| /u-boot/arch/powerpc/lib/ |
| A D | ppcstring.S | 25 addi r6,r3,-1
29 stbu r0,1(r6)
72 addi r6,r3,-4
75 stwu r4,4(r6)
77 andi. r0,r6,3
79 subf r6,r0,r6
89 addi r6,r6,3
111 stw r7,4(r6)
124 addi r6,r6,3
133 stb r7,4(r6)
[all …]
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| A D | _ashldi3.S | 33 subfic r6,r5,32
36 srw r6,r4,r6 # t1 = count > 31 ? 0 : LSW >> (32-count)
38 or r3,r3,r6 # MSW |= t1
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| A D | _lshrdi3.S | 33 subfic r6,r5,32
36 slw r6,r3,r6 # t1 = count > 31 ? 0 : MSW << (32-count)
38 or r4,r4,r6 # LSW |= t1
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| A D | _ashrdi3.S | 33 subfic r6,r5,32
36 slw r6,r3,r6 # t1 = count > 31 ? 0 : MSW << (32-count)
39 or r4,r4,r6 # LSW |= t1
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| /u-boot/arch/microblaze/cpu/ |
| A D | start.S | 69 cmp r6, r5, r4
70 beqi r6, 3f
75 bnei r6, 2b
113 swi r6, r1, 12
143 sw r6, r1, r0
148 sh r6, r0, r8
157 sw r6, r1, r0
182 sh r6, r0, r8
190 sw r6, r1, r0
195 sh r6, r0, r8
[all …]
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| /u-boot/arch/nios2/cpu/ |
| A D | start.S | 65 mov r6, r0
66 1: initd 0(r6)
67 add r6, r6, r4
68 bltu r6, r5, 1b
87 ori r6, r6, %lo(CONFIG_SYS_MONITOR_LEN)
88 add r6, r6, r5
93 bne r5, r6, 2b
167 movhi r6, %hi(__bss_end)
168 ori r6, r6, %lo(__bss_end)
169 beq r5, r6, 5f
[all …]
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| /u-boot/arch/arm/mach-tegra/ |
| A D | psci.S | 39 mov r6, lr
63 bx r6
76 ldr r6, =TEGRA_FLOW_CTRL_BASE
80 str r5, [r6, r2]
87 push {r4, r5, r6, lr}
96 ldr r6, =TEGRA_RESET_EXCEPTION_VECTOR
98 str r5, [r6]
102 ldr r6, =TEGRA_FLOW_CTRL_BASE
104 str r5, [r6, r2]
107 pop {r4, r5, r6, pc}
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| /u-boot/arch/arm/mach-imx/mx7/ |
| A D | psci-suspend.S | 41 mov r6, r2, lsl r0
42 orr r5, r5, r6 @ Reg = (Temp<<WayShift)|(NumSets<<SetShift)
56 mov r6, #0x0
57 mcr p15, 0, r6, c7, c5, 0
58 mcr p15, 0, r6, c7, c5, 6
60 mov r6, #0x1800
61 mcr p15, 0, r6, c1, c0, 0
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| /u-boot/board/armltd/integrator/ |
| A D | lowlevel_init.S | 109 stmfd r13!,{r4-r6,lr}
131 mov r6, #0x2 /* store size and CAS latency of 2 */
137 mov r6, #0x6
143 mov r6, #0xa
149 mov r6, #0xe
156 mov r6, #0x12
162 orr r6, r6, r3 /* OR in size and CAS latency */
163 str r6, [r0, #OS_SDRAM] /* store SDRAM parameters */
167 ldmfd r13!,{r4-r6,pc} /* back to caller */
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| /u-boot/arch/arm/cpu/armv7/ls102xa/ |
| A D | psci.S | 117 push {r4, r5, r6, lr}
154 mov r6, #0x4
155 mul r6, r6, r1
156 add r2, r0, r6
174 mov r6, #1
175 lsl r6, r6, r1 @ 32 bytes per CPU
177 rev r6, r6
178 orr r2, r2, r6
182 ldr r6, =psci_cpu_entry
183 rev r6, r6
[all …]
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| /u-boot/arch/nds32/cpu/n1213/ag101/ |
| A D | lowlevel_init.S | 241 la $r6, _end@GOTOFF
245 blt $r5, $r6, 1b
268 lwi $r6, [$r5]
270 and $r6 ,$r4, $r6
272 or $r6, $r4, $r6
273 swi $r6, [$r5]
281 li $r6, 0xffffff
282 and $r5, $r5, $r6
283 li $r6, 0x80000000
284 or $r5, $r5, $r6
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| /u-boot/post/lib_powerpc/ |
| A D | asm.S | 23 stmw r6, 0(r1)
30 lmw r6, 0(r1)
51 mr r5, r6
73 mr r4, r6
119 mr r3, r6
149 mr r3, r6
175 mr r5, r6
214 stwu r6, -4(r1)
264 mr r3, r6
291 mr r6, r7
[all …]
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| /u-boot/board/nokia/rx51/ |
| A D | lowlevel_init.S | 105 ldr r6, imagesize
115 cmp r5, r6
128 add r4, r0, r6
133 add r5, r5, r6
173 add r2, r1, r6
177 addlo r1, r0, r6 /* r1 - end of u-boot before */
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| /u-boot/board/armadeus/apf27/ |
| A D | lowlevel_init.S | 100 ldr r6,=0x7 /* load loop counter */
102 subs r6,r6,#1
137 ldr r6,=0x7 /* load loop counter */
139 subs r6,r6,#1
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| /u-boot/arch/arm/mach-mediatek/mt7623/ |
| A D | lowlevel_init.S | 11 ldr r6, =preloader_param
12 str r4, [r6]
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| /u-boot/arch/sh/lib/ |
| A D | udiv_qrnnd.S | 25 cmp/hi r6,r0
28 div1 r6,r0
32 add r6,r0
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| A D | movmem.S | 28 shll2 r6
34 add #-64,r6
36 tst r6,r6
40 cmp/pl r6
49 add r6,r0
192 dt r6
201 dt r6
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| A D | start.S | 24 mov.l ._reloc_dst_end, r6
34 add r0, r6
40 cmp/hs r6, r4
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| /u-boot/arch/powerpc/cpu/mpc86xx/ |
| A D | cache.S | 82 mr r6,r3
88 2: icbi 0,r6
89 addi r6,r6,CACHE_LINE_SIZE
128 mr r6,r3
134 1: icbi 0,r6
135 addi r6,r6,CACHE_LINE_SIZE
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| /u-boot/arch/arm/lib/ |
| A D | memcpy.S | 94 4: ldr8w r1, r3, r4, r5, r6, r7, r8, ip, lr, abort=20f
96 str8w r0, r3, r4, r5, r6, r7, r8, ip, lr, abort=20f
115 ldr1w r1, r6, abort=20f
133 str1w r0, r6, abort=20f
194 13: ldr4w r1, r4, r5, r6, r7, abort=19f
202 orr r5, r5, r6, lspush #\push
203 mov r6, r6, lspull #\pull
204 orr r6, r6, r7, lspush #\push
213 str8w r0, r3, r4, r5, r6, r7, r8, r9, ip, , abort=19f
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| A D | uldivmod.S | 23 D_0 .req r6
38 stmfd sp!, {r4, r5, r6, r7, THUMB(TMP,) lr}
156 ldmfd sp!, {r4, r5, r6, r7, THUMB(TMP,) pc}
166 ldmfd sp!, {r4, r5, r6, r7, THUMB(TMP,) pc}
193 ldmfd sp!, {r4, r5, r6, r7, THUMB(TMP,) pc}
233 ldmfd sp!, {r4, r5, r6, r7, THUMB(TMP,) pc}
243 ldmfd sp!, {r4, r5, r6, r7, THUMB(TMP,) pc}
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| /u-boot/arch/arm/cpu/armv7/ |
| A D | cache_v7_asm.S | 53 THUMB( lsl r6, r4, r5 )
54 THUMB( orr r11, r10, r6 ) @ factor way and cache number into r11
56 THUMB( lsl r6, r9, r2 )
57 THUMB( orr r11, r11, r6 ) @ factor index number into r11
123 THUMB( lsl r6, r4, r5 )
124 THUMB( orr r11, r10, r6 ) @ factor way and cache number into r11
126 THUMB( lsl r6, r9, r2 )
127 THUMB( orr r11, r11, r6 ) @ factor index number into r11
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| /u-boot/arch/nds32/include/asm/ |
| A D | macro.h | 50 li $r6, \data
51 or $r5, $r5, $r6
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| /u-boot/arch/powerpc/cpu/mpc85xx/ |
| A D | start.S | 456 0, r6
467 0, r6
1025 ori r6,r6,FSL_BOOKE_MAS0(1, 15, 0)@l
1033 0, r6
1043 0, r6
1059 0, r6
1070 0, r6
1087 0, r6
1091 ori r6,r6,MSR_IS|MSR_DS|MSR_DE@l
1588 4: cmpwi r6,0
[all …]
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