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Searched refs:rate (Results 1 – 25 of 354) sorted by relevance

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/u-boot/drivers/clk/renesas/
A Dclk-rcar-gen3.c167 u64 rate = 0; in gen3_clk_get_rate64() local
182 return rate; in gen3_clk_get_rate64()
212 return rate; in gen3_clk_get_rate64()
220 return rate; in gen3_clk_get_rate64()
229 return rate; in gen3_clk_get_rate64()
237 return rate; in gen3_clk_get_rate64()
246 return rate; in gen3_clk_get_rate64()
254 return rate; in gen3_clk_get_rate64()
261 return rate; in gen3_clk_get_rate64()
299 rate /= 5; in gen3_clk_get_rate64()
[all …]
A Dclk-rcar-gen2.c99 return rate; in gen2_clk_get_rate()
112 return rate; in gen2_clk_get_rate()
119 return rate; in gen2_clk_get_rate()
129 return rate; in gen2_clk_get_rate()
137 return rate; in gen2_clk_get_rate()
144 return rate; in gen2_clk_get_rate()
162 return rate; in gen2_clk_get_rate()
169 return rate; in gen2_clk_get_rate()
176 return rate; in gen2_clk_get_rate()
185 return rate; in gen2_clk_get_rate()
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/u-boot/drivers/clk/rockchip/
A Dclk_pll.c173 if (rate_table->rate == rate) in rockchip_get_pll_settings()
177 if (rate_table->rate != rate) in rockchip_get_pll_settings()
190 if (!rate) { in rk3036_pll_set_rate()
196 __func__, rate->rate, rate->fbdiv, rate->postdiv1, rate->refdiv); in rk3036_pll_set_rate()
198 __func__, rate->rate, rate->postdiv2, rate->dsmpd, rate->frac); in rk3036_pll_set_rate()
256 ulong rate; in rk3036_pll_get_rate() local
292 return rate; in rk3036_pll_get_rate()
303 ulong rate = 0; in rockchip_pll_get_rate() local
318 return rate; in rockchip_pll_get_rate()
353 if (ps->rate == rate) in rockchip_get_cpu_settings()
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/u-boot/arch/mips/mach-pic32/
A Dcpu.c28 static ulong rate(int id) in rate() function
33 ulong rate; in rate() local
46 rate = clk_get_rate(&clk); in rate()
50 return rate; in rate()
55 return rate(PB7CLK); in clk_get_cpu_rate()
64 ulong rate; in prefetch_init() local
74 if (rate < 66) in prefetch_init()
76 else if (rate < 133) in prefetch_init()
81 if (rate <= 83) in prefetch_init()
83 else if (rate <= 166) in prefetch_init()
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/u-boot/arch/arm/mach-imx/mx7ulp/
A Dscg.c211 rate = rate / val * 18; in scg_apll_pfd_get_rate()
261 rate = rate / val * 18; in scg_spll_pfd_get_rate()
281 rate = rate / (val + 1); in scg_apll_get_rate()
285 rate = rate / (val + 1); in scg_apll_get_rate()
311 rate = rate / (val + 1); in scg_spll_get_rate()
315 rate = rate / (val + 1); in scg_spll_get_rate()
374 rate = rate / (val + 1); in scg_nic_get_rate()
397 rate = rate / (val + 1); in scg_nic_get_rate()
425 rate = rate / (val + 1); in scg_nic_get_rate()
469 rate = rate / (val + 1); in scg_sys_get_rate()
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/u-boot/test/dm/
A Dclk_ccf.c23 long long rate; in dm_test_clk_ccf() local
46 ut_asserteq(rate, 20000000); in dm_test_clk_ccf()
55 ut_asserteq(rate, 20000000); in dm_test_clk_ccf()
64 ut_asserteq(rate, 60000000); in dm_test_clk_ccf()
66 rate = clk_get_rate(clk); in dm_test_clk_ccf()
67 ut_asserteq(rate, 60000000); in dm_test_clk_ccf()
75 rate = clk_get_rate(clk); in dm_test_clk_ccf()
76 ut_asserteq(rate, 80000000); in dm_test_clk_ccf()
90 rate = clk_get_rate(clk); in dm_test_clk_ccf()
99 rate = clk_get_rate(clk); in dm_test_clk_ccf()
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/u-boot/arch/arm/mach-zynq/
A Dclk.c40 ulong rate; in set_cpu_clk_info() local
54 rate = clk_get_rate(&clk) / 1000000; in set_cpu_clk_info()
56 gd->bd->bi_ddr_freq = rate; in set_cpu_clk_info()
58 gd->bd->bi_arm_freq = rate; in set_cpu_clk_info()
88 unsigned long rate; in soc_clk_dump() local
95 rate = clk_get_rate(&clk); in soc_clk_dump()
99 if ((rate == (unsigned long)-ENOSYS) || in soc_clk_dump()
100 (rate == (unsigned long)-ENXIO)) in soc_clk_dump()
103 printf("%10s%20lu\n", name, rate); in soc_clk_dump()
/u-boot/drivers/clk/imx/
A Dclk-pll14xx.c62 if (rate == rate_table[i].rate) in imx_get_pll_settings()
116 return rate->mdiv != old_mdiv || rate->pdiv != old_pdiv; in clk_pll1416x_mp_change()
128 return rate->mdiv != old_mdiv || rate->pdiv != old_pdiv || in clk_pll1443x_mpk_change()
129 rate->kdiv != old_kdiv; in clk_pll1443x_mpk_change()
141 return rate->mdiv != old_mdiv || rate->pdiv != old_pdiv || in clk_pll1443x_mp_change()
142 rate->kdiv != old_kdiv; in clk_pll1443x_mp_change()
161 if (!rate) { in clk_pll1416x_set_rate()
191 div_val = (rate->mdiv << MDIV_SHIFT) | (rate->pdiv << PDIV_SHIFT) | in clk_pll1416x_set_rate()
192 (rate->sdiv << SDIV_SHIFT); in clk_pll1416x_set_rate()
227 if (!rate) { in clk_pll1443x_set_rate()
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/u-boot/drivers/clk/aspeed/
A Dclk_ast2600.c260 uint32_t rate = 0; in ast2600_get_uxclk_in_rate() local
280 return rate; in ast2600_get_uxclk_in_rate()
285 uint32_t rate = 0; in ast2600_get_huxclk_in_rate() local
305 return rate; in ast2600_get_huxclk_in_rate()
334 uint32_t rate = 0; in ast2600_get_sdio_clk_rate() local
359 uint32_t rate = 0; in ast2600_get_uart_clk_rate() local
418 return rate; in ast2600_get_uart_clk_rate()
424 ulong rate = 0; in ast2600_clk_get_rate() local
478 return rate; in ast2600_clk_get_rate()
568 mpll.out = rate; in ast2600_configure_ddr()
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/u-boot/drivers/cpu/
A Dat91_cpu.c80 ulong rate; in at91_cpu_probe() local
87 rate = clk_get_rate(&clk); in at91_cpu_probe()
88 if (!rate) in at91_cpu_probe()
90 plat->cpufreq_mhz = DIV_ROUND_CLOSEST_ULL(rate, 1000000); in at91_cpu_probe()
96 rate = clk_get_rate(&clk); in at91_cpu_probe()
97 if (!rate) in at91_cpu_probe()
99 plat->mckfreq_mhz = DIV_ROUND_CLOSEST_ULL(rate, 1000000); in at91_cpu_probe()
105 rate = clk_get_rate(&clk); in at91_cpu_probe()
106 if (!rate) in at91_cpu_probe()
108 plat->xtalfreq_mhz = DIV_ROUND_CLOSEST_ULL(rate, 1000000); in at91_cpu_probe()
/u-boot/drivers/clk/ti/
A Dclk-am3-dpll.c45 rate, priv->max_rate); in clk_ti_am3_dpll_round_rate()
46 rate = priv->max_rate; in clk_ti_am3_dpll_round_rate()
50 err = rate; in clk_ti_am3_dpll_round_rate()
51 err_min = rate; in clk_ti_am3_dpll_round_rate()
56 err = abs(r - rate); in clk_ti_am3_dpll_round_rate()
65 } else if (r > rate) { in clk_ti_am3_dpll_round_rate()
127 u64 rate; in clk_ti_am3_dpll_get_rate() local
141 return rate; in clk_ti_am3_dpll_get_rate()
151 do_div(rate, n + 1); in clk_ti_am3_dpll_get_rate()
152 dev_dbg(clk->dev, "rate=%lld\n", rate); in clk_ti_am3_dpll_get_rate()
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A Dclk-am3-dpll-x2.c23 unsigned long rate; in clk_ti_am3_dpll_x2_get_rate() local
25 rate = clk_get_rate(&priv->parent); in clk_ti_am3_dpll_x2_get_rate()
26 if (IS_ERR_VALUE(rate)) in clk_ti_am3_dpll_x2_get_rate()
27 return rate; in clk_ti_am3_dpll_x2_get_rate()
29 rate *= 2; in clk_ti_am3_dpll_x2_get_rate()
30 dev_dbg(clk->dev, "rate=%ld\n", rate); in clk_ti_am3_dpll_x2_get_rate()
31 return rate; in clk_ti_am3_dpll_x2_get_rate()
A Dclk-divider.c72 ulong rate) in _div_round_up() argument
92 ulong rate) in _div_round() argument
112 if (!rate) in clk_ti_divider_best_div()
113 rate = 1; in clk_ti_divider_best_div()
137 if ((rate * i) == parent_rate) { in clk_ti_divider_best_div()
140 rate, rate, i); in clk_ti_divider_best_div()
145 MULT_ROUND_UP(rate, i)); in clk_ti_divider_best_div()
150 if (r <= rate && r > best_rate) { in clk_ti_divider_best_div()
154 if (best_rate == rate) in clk_ti_divider_best_div()
215 ulong rate, parent_rate; in clk_ti_divider_get_rate() local
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/u-boot/arch/arm/mach-socfpga/
A Dclock_manager_agilex.c24 ulong rate; in cm_get_rate_dm() local
38 rate = clk_get_rate(&clk); in cm_get_rate_dm()
42 if ((rate == (unsigned long)-ENOSYS) || in cm_get_rate_dm()
43 (rate == (unsigned long)-ENXIO) || in cm_get_rate_dm()
44 (rate == (unsigned long)-EIO)) { in cm_get_rate_dm()
46 __func__, id, rate); in cm_get_rate_dm()
50 return rate; in cm_get_rate_dm()
/u-boot/drivers/clk/meson/
A Dg12a.c284 return rate; in meson_div_get_rate()
297 if (current_rate == rate) in meson_div_set_rate()
692 ulong rate; in meson_pll_get_rate() local
737 rate -= frac_rate; in meson_pll_get_rate()
739 rate += frac_rate; in meson_pll_get_rate()
777 ulong rate; in meson_clk_get_rate_by_id() local
781 rate = XTAL_RATE; in meson_clk_get_rate_by_id()
857 return rate; in meson_clk_get_rate_by_id()
898 if (current_rate == rate) in meson_clk_set_rate_by_id()
928 rate, current_rate); in meson_clk_set_rate_by_id()
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A Dgxbb.c274 unsigned int rate, parent_rate; in meson_div_get_rate() local
311 rate = parent_rate / (reg + 1); in meson_div_get_rate()
315 return rate; in meson_div_get_rate()
328 if (current_rate == rate) in meson_div_set_rate()
728 ulong rate; in meson_clk_get_rate_by_id() local
733 rate = meson_pll_get_rate(clk, id); in meson_clk_get_rate_by_id()
756 rate = meson_clk81_get_rate(clk); in meson_clk_get_rate_by_id()
790 rate = meson_clk81_get_rate(clk); in meson_clk_get_rate_by_id()
797 return rate; in meson_clk_get_rate_by_id()
813 if (current_rate == rate) in meson_clk_set_rate_by_id()
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/u-boot/arch/arm/mach-nexell/
A Dclock.c527 return rate; in core_get_rate()
532 return clk->rate; in core_set_rate()
557 return rate; in clk_divide()
570 ret = rate / div; in clk_divide()
650 rate = pll->clk.rate; in clk_round_rate()
653 if (!rate) in clk_round_rate()
657 rate = clk_divide(rate, request, 2, &div[i]); in clk_round_rate()
673 rate_hz = rate; in clk_round_rate()
697 rate); in clk_round_rate()
702 return clk->rate; in clk_round_rate()
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/u-boot/drivers/clk/
A Dclk-composite.c51 struct clk *rate = composite->rate; in clk_composite_recalc_rate() local
53 if (rate && rate_ops) in clk_composite_recalc_rate()
54 return rate_ops->get_rate(rate); in clk_composite_recalc_rate()
64 struct clk *clk_rate = composite->rate; in clk_composite_set_rate()
66 if (rate && rate_ops) in clk_composite_set_rate()
102 struct clk *rate, in clk_register_composite() argument
125 if (rate && rate_ops) { in clk_register_composite()
131 composite->rate = rate; in clk_register_composite()
133 rate->data = (ulong)composite; in clk_register_composite()
158 if (composite->rate) in clk_register_composite()
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A Dclk_pic32.c192 do_div(frac, rate); in pic32_set_refclk()
288 u64 rate; in pic32_get_mpll_rate() local
297 do_div(rate, odiv1); in pic32_get_mpll_rate()
298 do_div(rate, odiv2); in pic32_get_mpll_rate()
300 return (ulong)rate; in pic32_get_mpll_rate()
325 ulong rate, pll_hz; in pic32_clk_init() local
337 if (rate) in pic32_clk_init()
348 ulong rate; in pic32_get_rate() local
364 rate = 0; in pic32_get_rate()
368 return rate; in pic32_get_rate()
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A Dclk-hsdk-cgu.c194 const u32 rate; member
261 unsigned long rate,
426 u64 rate; in pll_get() local
451 do_div(rate, idiv * odiv); in pll_get()
453 return rate; in pll_get()
463 if (pll_cfg[0].rate == 0) in hsdk_pll_round_rate()
469 if (abs(rate - pll_cfg[i].rate) < abs(rate - best_rate)) in hsdk_pll_round_rate()
479 unsigned long rate, in hsdk_pll_comm_update_rate() argument
499 unsigned long rate, in hsdk_pll_core_update_rate() argument
582 ret = pll_set(sclk, rate); in cpu_clk_set()
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A Dclk_fixed_factor.c25 uint64_t rate; in clk_fixed_factor_get_rate() local
28 rate = clk_get_rate(&ff->parent); in clk_fixed_factor_get_rate()
29 if (IS_ERR_VALUE(rate)) in clk_fixed_factor_get_rate()
30 return rate; in clk_fixed_factor_get_rate()
32 do_div(rate, ff->div); in clk_fixed_factor_get_rate()
34 return rate * ff->mult; in clk_fixed_factor_get_rate()
A Dclk_sandbox.c15 ulong rate[SANDBOX_CLK_ID_COUNT]; member
30 return priv->rate[clk->id]; in sandbox_clk_get_rate()
33 static ulong sandbox_clk_round_rate(struct clk *clk, ulong rate) in sandbox_clk_round_rate() argument
43 if (!rate) in sandbox_clk_round_rate()
46 return rate; in sandbox_clk_round_rate()
49 static ulong sandbox_clk_set_rate(struct clk *clk, ulong rate) in sandbox_clk_set_rate() argument
60 if (!rate) in sandbox_clk_set_rate()
63 old_rate = priv->rate[clk->id]; in sandbox_clk_set_rate()
64 priv->rate[clk->id] = rate; in sandbox_clk_set_rate()
160 return priv->rate[id]; in sandbox_clk_query_rate()
/u-boot/arch/arm/mach-tegra/
A Demc.c26 unsigned rate; in board_emc_init() local
31 rate = EMC_SDRAM_RATE_T20; in board_emc_init()
34 rate = EMC_SDRAM_RATE_T25; in board_emc_init()
37 return tegra_set_emc(gd->fdt_blob, rate); in board_emc_init()
/u-boot/arch/arm/cpu/armv7/bcm281xx/
A Dclk-core.c173 diff = rate; in peri_clk_set_rate()
184 div = ref->clk.rate / rate; in peri_clk_set_rate()
195 c->rate = new_rate; in peri_clk_set_rate()
201 c->name, c->rate, c->div, c->sel, c->parent->rate); in peri_clk_set_rate()
243 c->rate = c->parent->rate / c->div; in peri_clk_get_rate()
245 c->parent->rate, div, c->sel, c->rate); in peri_clk_get_rate()
247 return c->rate; in peri_clk_get_rate()
326 return c->rate; in ccu_clk_get_rate()
386 return c->rate; in bus_clk_get_rate()
481 unsigned long rate; in clk_get_rate() local
[all …]
/u-boot/arch/arm/cpu/armv7/bcm235xx/
A Dclk-core.c173 diff = rate; in peri_clk_set_rate()
184 div = ref->clk.rate / rate; in peri_clk_set_rate()
195 c->rate = new_rate; in peri_clk_set_rate()
201 c->name, c->rate, c->div, c->sel, c->parent->rate); in peri_clk_set_rate()
243 c->rate = c->parent->rate / c->div; in peri_clk_get_rate()
245 c->parent->rate, div, c->sel, c->rate); in peri_clk_get_rate()
247 return c->rate; in peri_clk_get_rate()
326 return c->rate; in ccu_clk_get_rate()
386 return c->rate; in bus_clk_get_rate()
481 unsigned long rate; in clk_get_rate() local
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