| /u-boot/arch/arm/mach-exynos/ |
| A D | clock.c | 642 unsigned int ratio; in exynos4_get_pwm_clk() local
666 ratio = ratio & 0xf; in exynos4_get_pwm_clk()
669 ratio = 8; in exynos4_get_pwm_clk()
685 ratio = 8; in exynos4x12_get_pwm_clk()
732 ratio = (ratio >> (dev_index << 2)) & 0xf; in exynos4_get_uart_clk()
777 ratio = (ratio >> (dev_index << 2)) & 0xf; in exynos4x12_get_uart_clk()
826 ratio = (ratio >> shift) & 0xf; in exynos4_get_mmc_clk()
947 ratio = ratio & 0xf; in exynos4_get_lcd_clk()
989 ratio = ratio & 0xf; in exynos5_get_lcd_clk()
1023 ratio = ratio & 0xf; in exynos5420_get_lcd_clk()
[all …]
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| /u-boot/arch/x86/cpu/intel_common/ |
| A D | acpi.c | 224 static int calculate_power(int tdp, int p1_ratio, int ratio) in calculate_power() argument
235 m = (110000 - ((p1_ratio - ratio) * 625)) / 11; in calculate_power()
238 power = ((ratio * 100000 / p1_ratio) / 100); in calculate_power()
250 int ratio, power, clock, clock_max; in generate_p_state_entries() local
312 for (ratio = ratio_min + ((num_entries - 1) * ratio_step); in generate_p_state_entries()
313 ratio >= ratio_min; ratio -= ratio_step) { in generate_p_state_entries()
315 power = calculate_power(power_max, ratio_max, ratio); in generate_p_state_entries()
316 clock = (ratio * cpu_get_bus_clock_khz()) / 1000; in generate_p_state_entries()
322 ratio << 8, /* control */ in generate_p_state_entries()
323 ratio << 8); /* status */ in generate_p_state_entries()
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| /u-boot/arch/arm/cpu/armv7/ls102xa/ |
| A D | clock.c | 41 uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS]; in get_sys_info() local
57 ratio[i] = (in_be32(&clk->pllcgsr[i].pllcngsr) >> 1) & 0x3f; in get_sys_info()
58 if (ratio[i] > 4) in get_sys_info()
59 freq_c_pll[i] = sysclk * ratio[i]; in get_sys_info()
61 freq_c_pll[i] = sys_info->freq_systembus * ratio[i]; in get_sys_info()
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| /u-boot/arch/x86/include/asm/ |
| A D | speedstep.h | 28 uint8_t ratio:6; member
54 ((uint16_t)(state).ratio << SPEEDSTEP_RATIO_SHIFT) | \
57 ((uint8_t)(state).ratio * 2) + (state).nonint)
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| /u-boot/arch/arm/cpu/armv8/fsl-layerscape/ |
| A D | fsl_lsch2_speed.c | 54 uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS]; in get_sys_info() local
84 ratio[i] = (in_be32(&clk->pllcgsr[i].pllcngsr) >> 1) & 0xff; in get_sys_info()
85 if (ratio[i] > 4) in get_sys_info()
86 freq_c_pll[i] = cluster_clk * ratio[i]; in get_sys_info()
88 freq_c_pll[i] = sys_info->freq_systembus * ratio[i]; in get_sys_info()
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| A D | fsl_lsch3_speed.c | 74 uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS]; in get_sys_info() local
118 ratio[i] = (in_le32(offset) >> 1) & 0x3f; in get_sys_info()
119 freq_c_pll[i] = sysclk * ratio[i]; in get_sys_info()
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| /u-boot/drivers/timer/ |
| A D | tsc_timer.c | 153 u32 lo, hi, ratio, freq_id, freq; in cpu_mhz_from_msr() local
166 ratio = (lo >> 8) & 0xff; in cpu_mhz_from_msr()
169 ratio = (hi >> 8) & 0x1f; in cpu_mhz_from_msr()
171 debug("Maximum core-clock to bus-clock ratio: 0x%x\n", ratio); in cpu_mhz_from_msr()
187 res = freq * ratio / 1000; in cpu_mhz_from_msr()
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| /u-boot/drivers/clk/analogbits/ |
| A D | wrpll-cln28hpc.c | 224 unsigned long ratio; in wrpll_configure_for_rate() local
261 ratio = div64_u64((target_vco_rate << ROUND_SHIFT), parent_rate); in wrpll_configure_for_rate()
273 f_pre_div = ratio * r; in wrpll_configure_for_rate()
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| /u-boot/arch/x86/cpu/ivybridge/ |
| A D | model_206ax.c | 332 uint ratio; in set_max_ratio() local
338 ratio = msr.lo & 0xff; in set_max_ratio()
342 ratio = (msr.lo & 0xff00) >> 8; in set_max_ratio()
344 cpu_set_perf_control(ratio); in set_max_ratio()
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| /u-boot/drivers/fpga/ |
| A D | socfpga_gen5.c | 20 static void fpgamgr_set_cd_ratio(unsigned long ratio) in fpgamgr_set_cd_ratio() argument
24 (ratio & 0x3) << FPGAMGRREGS_CTRL_CDRATIO_LSB); in fpgamgr_set_cd_ratio()
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| A D | socfpga_arria10.c | 39 static void fpgamgr_set_cd_ratio(unsigned long ratio);
136 static void fpgamgr_set_cd_ratio(unsigned long ratio) in fpgamgr_set_cd_ratio() argument
142 (ratio << ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_LSB) & in fpgamgr_set_cd_ratio()
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| /u-boot/drivers/clk/kendryte/ |
| A D | pll.c | 249 u64 ratio, inv_ratio; /* fixed point 32.32 ratio of the rates */ in k210_pll_calc_config() local
265 ratio = DIV_ROUND_CLOSEST_ULL((u64)rate << 32, rate_in); in k210_pll_calc_config()
268 if (rate > rate_in && ratio > (64ULL << 32)) in k210_pll_calc_config()
315 f = (r * od * ratio + BIT(31)) >> 32; in k210_pll_calc_config()
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| /u-boot/arch/powerpc/cpu/mpc85xx/ |
| A D | speed.c | 76 uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS]; in get_sys_info() local
155 ratio[i] = (in_be32(&clk->pllcgsr[i].pllcngsr) >> 1) & 0x3f; in get_sys_info()
156 if (ratio[i] > 4) in get_sys_info()
157 freq_c_pll[i] = sysclk * ratio[i]; in get_sys_info()
159 freq_c_pll[i] = sys_info->freq_systembus * ratio[i]; in get_sys_info()
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| /u-boot/lib/lzma/ |
| A D | lzma.txt | 9 compression ratio and very fast decompression.
12 It was improved in way of maximum increasing of compression ratio,
197 Usually big number gives a little bit better compression ratio
215 ratio, but they often works pretty fast in combination with
255 Compression ratio hints
261 To increase the compression ratio for LZMA compressing it's desirable
270 You can increase the compression ratio for some data types, using
272 increase the compression ratio on 5-10% for code for those CPU ISAs:
277 You can check the compression ratio gain of these filters with such
292 since compression ratio with filtering is higher.
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| A D | history.txt | 135 - Compression ratio was improved in -a2 mode
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| /u-boot/doc/device-tree-bindings/exynos/ |
| A D | dwmmc.txt | 35 . DIVRATIO: Clock Divide ratio select.
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| /u-boot/drivers/video/rockchip/ |
| A D | Kconfig | 70 16,18, 24 bits per pixel with up to 2k resolution ratio.
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| /u-boot/drivers/ddr/altera/ |
| A D | sequencer.c | 111 u32 ratio; in phy_mgr_initialize() local
134 ratio = seq->rwcfg->mem_dq_per_read_dqs / in phy_mgr_initialize()
136 seq->param.read_correct_mask_vg = (1 << ratio) - 1; in phy_mgr_initialize()
137 seq->param.write_correct_mask_vg = (1 << ratio) - 1; in phy_mgr_initialize()
465 const int ratio = seq->rwcfg->mem_if_read_dqs_width / in scc_mgr_set_oct_out1_delay() local
467 const int base = write_group * ratio; in scc_mgr_set_oct_out1_delay()
476 for (i = 0; i < ratio; i++) in scc_mgr_set_oct_out1_delay()
581 const int ratio = seq->rwcfg->mem_if_read_dqs_width / in scc_mgr_load_dqs_for_write_group() local
583 const int base = write_group * ratio; in scc_mgr_load_dqs_for_write_group()
592 for (i = 0; i < ratio; i++) in scc_mgr_load_dqs_for_write_group()
[all …]
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| /u-boot/drivers/clk/ |
| A D | mpc83xx_clk.h | 21 enum ratio { enum
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| /u-boot/doc/device-tree-bindings/video/ |
| A D | exynos-fb.txt | 56 samsung,sclk-div: parent_clock/source_clock ratio
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| /u-boot/arch/arm/dts/ |
| A D | am335x-brppt1-mmc.dts | 296 ti,zx-cutoff-ratio = <40>;
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| A D | am335x-brppt1-spi.dts | 317 ti,zx-cutoff-ratio = <40>;
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| A D | am335x-brppt1-nand.dts | 286 ti,zx-cutoff-ratio = <40>;
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| A D | k3-j721e-common-proc-board.dts | 624 auxclk-fs-ratio = <256>;
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| /u-boot/arch/arm/cpu/armv8/fsl-layerscape/doc/ |
| A D | README.falcon | 150 in U-Boot. Normal U-Boot sets the MDC ratio to generate a proper clock signal.
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