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Searched refs:ref_clk_satr (Results 1 – 1 of 1) sorted by relevance

/u-boot/drivers/ddr/marvell/a38x/
A Dmv_ddr_plat.c391 u32 reg, ref_clk_satr; in mv_ddr_sar_freq_get() local
398 ref_clk_satr = reg_read(DEVICE_SAMPLE_AT_RESET2_REG); in mv_ddr_sar_freq_get()
399 if (((ref_clk_satr >> DEVICE_SAMPLE_AT_RESET2_REG_REFCLK_OFFSET) & 0x1) == in mv_ddr_sar_freq_get()
485 u32 reg, ref_clk_satr; in ddr3_tip_a38x_get_medium_freq() local
492 ref_clk_satr = reg_read(DEVICE_SAMPLE_AT_RESET2_REG); in ddr3_tip_a38x_get_medium_freq()
493 if (((ref_clk_satr >> DEVICE_SAMPLE_AT_RESET2_REG_REFCLK_OFFSET) & 0x1) == in ddr3_tip_a38x_get_medium_freq()
735 u32 sar_val, ref_clk_satr; in ddr3_tip_a38x_set_divider() local
751 ref_clk_satr = reg_read(DEVICE_SAMPLE_AT_RESET2_REG); in ddr3_tip_a38x_set_divider()
752 if (((ref_clk_satr >> DEVICE_SAMPLE_AT_RESET2_REG_REFCLK_OFFSET) & 0x1) == in ddr3_tip_a38x_set_divider()

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