| /u-boot/drivers/clk/rockchip/ |
| A D | clk_pll.c | 130 rate_table->refdiv = fin_hz / clk_gcd; in rockchip_pll_clk_set_by_auto()
138 rate_table->refdiv, in rockchip_pll_clk_set_by_auto()
147 rate_table->refdiv = fin_hz / MHZ / clk_gcd; in rockchip_pll_clk_set_by_auto()
150 rate_table->refdiv, rate_table->fbdiv); in rockchip_pll_clk_set_by_auto()
156 fin_64 = fin_64 / rate_table->refdiv; in rockchip_pll_clk_set_by_auto()
196 __func__, rate->rate, rate->fbdiv, rate->postdiv1, rate->refdiv); in rk3036_pll_set_rate()
221 rate->refdiv << RK3036_PLLCON1_REFDIV_SHIFT)); in rk3036_pll_set_rate()
254 u32 refdiv, fbdiv, postdiv1, postdiv2, dsmpd, frac; in rk3036_pll_get_rate() local
275 refdiv = (con & RK3036_PLLCON1_REFDIV_MASK) >> in rk3036_pll_get_rate()
282 rate = (24 * fbdiv / (refdiv * postdiv1 * postdiv2)) * 1000000; in rk3036_pll_get_rate()
[all …]
|
| A D | clk_rk3128.c | 34 .refdiv = _refdiv,\
49 uint vco_hz = OSC_HZ / 1000 * div->fbdiv / div->refdiv * 1000; in rkclk_set_pll()
53 pll, div->fbdiv, div->refdiv, div->postdiv1, in rkclk_set_pll()
68 div->refdiv << PLL_REFDIV_SHIFT)); in rkclk_set_pll()
82 u32 ref_khz = OSC_HZ / 1000, refdiv, fbdiv = 0; in pll_para_config() local
115 for (refdiv = 1; refdiv < max_refdiv && best_diff_khz; refdiv++) { in pll_para_config()
116 fref_khz = ref_khz / refdiv; in pll_para_config()
131 div->refdiv = refdiv; in pll_para_config()
245 u32 refdiv, fbdiv, postdiv1, postdiv2; in rkclk_pll_get_rate() local
274 refdiv = (con & PLL_REFDIV_MASK) >> PLL_REFDIV_SHIFT; in rkclk_pll_get_rate()
[all …]
|
| A D | clk_rk322x.c | 35 .refdiv = _refdiv,\
54 uint vco_hz = OSC_HZ / 1000 * div->fbdiv / div->refdiv * 1000; in rkclk_set_pll()
58 pll, div->fbdiv, div->refdiv, div->postdiv1, in rkclk_set_pll()
73 div->refdiv << PLL_REFDIV_SHIFT)); in rkclk_set_pll()
179 uint32_t refdiv, fbdiv, postdiv1, postdiv2; in rkclk_pll_get_rate() local
209 refdiv = (con & PLL_REFDIV_MASK) >> PLL_REFDIV_SHIFT; in rkclk_pll_get_rate()
210 return (24 * fbdiv / (refdiv * postdiv1 * postdiv2)) * 1000000; in rkclk_pll_get_rate()
333 {.refdiv = 1, .fbdiv = 50, .postdiv1 = 3, .postdiv2 = 1}; in rk322x_ddr_set_clk()
337 {.refdiv = 1, .fbdiv = 75, .postdiv1 = 3, .postdiv2 = 1}; in rk322x_ddr_set_clk()
341 {.refdiv = 1, .fbdiv = 100, .postdiv1 = 3, .postdiv2 = 1}; in rk322x_ddr_set_clk()
|
| A D | clk_rk3036.c | 37 .refdiv = _refdiv,\
56 uint vco_hz = OSC_HZ / 1000 * div->fbdiv / div->refdiv * 1000; in rkclk_set_pll()
61 pll, div->fbdiv, div->refdiv, div->postdiv1, in rkclk_set_pll()
74 div->refdiv << PLL_REFDIV_SHIFT)); in rkclk_set_pll()
177 uint32_t refdiv, fbdiv, postdiv1, postdiv2; in rkclk_pll_get_rate() local
207 refdiv = (con & PLL_REFDIV_MASK) >> PLL_REFDIV_SHIFT; in rkclk_pll_get_rate()
208 return (24 * fbdiv / (refdiv * postdiv1 * postdiv2)) * 1000000; in rkclk_pll_get_rate()
|
| A D | clk_rk3399.c | 41 u32 refdiv; member
53 .refdiv = _refdiv,\
328 u32 vco_khz = OSC_HZ / 1000 * div->fbdiv / div->refdiv; in rkclk_set_pll()
333 pll_con, div->fbdiv, div->refdiv, div->postdiv1, in rkclk_set_pll()
357 (div->refdiv << PLL_REFDIV_SHIFT)); in rkclk_set_pll()
370 u32 ref_khz = OSC_HZ / KHz, refdiv, fbdiv = 0; in pll_para_config() local
403 for (refdiv = 1; refdiv < max_refdiv && best_diff_khz; refdiv++) { in pll_para_config()
404 fref_khz = ref_khz / refdiv; in pll_para_config()
419 div->refdiv = refdiv; in pll_para_config()
843 {.refdiv = 1, .fbdiv = 12, .postdiv1 = 3, .postdiv2 = 2}; in rk3399_ddr_set_clk()
[all …]
|
| A D | clk_rv1108.c | 38 .refdiv = _refdiv,\
78 uint vco_hz = OSC_HZ / 1000 * div->fbdiv / div->refdiv * 1000; in rkclk_set_pll()
82 pll, div->fbdiv, div->refdiv, div->postdiv1, in rkclk_set_pll()
103 div->refdiv << REFDIV_SHIFT)); in rkclk_set_pll()
105 (div->refdiv << REFDIV_SHIFT)); in rkclk_set_pll()
126 uint32_t refdiv, fbdiv, postdiv1, postdiv2; in rkclk_pll_get_rate() local
140 refdiv = (con1 >> REFDIV_SHIFT) & REFDIV_MASK; in rkclk_pll_get_rate()
141 freq = (24 * fbdiv / (refdiv * postdiv1 * postdiv2)) * 1000000; in rkclk_pll_get_rate()
|
| A D | clk_px30.c | 42 .refdiv = _refdiv, \
101 u32 ref_khz = OSC_HZ / KHz, refdiv, fbdiv = 0; in pll_clk_set_by_auto() local
134 for (refdiv = 1; refdiv < max_refdiv && best_diff_khz; refdiv++) { in pll_clk_set_by_auto()
135 fref_khz = ref_khz / refdiv; in pll_clk_set_by_auto()
151 rate->refdiv = refdiv; in pll_clk_set_by_auto()
220 vco_hz = OSC_HZ / 1000 * rate->fbdiv / rate->refdiv * 1000; in rkclk_set_pll()
224 pll, rate->fbdiv, rate->refdiv, rate->postdiv1, in rkclk_set_pll()
246 rate->refdiv << PLL_REFDIV_SHIFT)); in rkclk_set_pll()
264 u32 refdiv, fbdiv, postdiv1, postdiv2; in rkclk_pll_get_rate() local
281 refdiv = (con & PLL_REFDIV_MASK) >> PLL_REFDIV_SHIFT; in rkclk_pll_get_rate()
[all …]
|
| A D | clk_rk3328.c | 26 u32 refdiv; member
38 .refdiv = _refdiv,\
246 u32 vco_khz = OSC_HZ / 1000 * div->fbdiv / div->refdiv; in rkclk_set_pll()
251 pll_con, div->fbdiv, div->refdiv, div->postdiv1, in rkclk_set_pll()
274 (div->refdiv << PLL_REFDIV_SHIFT)); in rkclk_set_pll()
|
| /u-boot/arch/mips/mach-ath79/ar934x/ |
| A D | clk.c | 37 u8 refdiv; member
150 pll_refdiv = pll_cfg->refdiv; in ar934x_pll_init()
159 pll_refdiv = pll_cfg->refdiv; in ar934x_pll_init()
238 const u32 refdiv = (regval >> AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT) & in ar934x_cpupll_to_hz() local
246 return (xtal * (nint + (nfrac >> 9))) / (refdiv * (1 << outdiv)); in ar934x_cpupll_to_hz()
253 const u32 refdiv = (regval >> AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT) & in ar934x_ddrpll_to_hz() local
261 return (xtal * (nint + (nfrac >> 9))) / (refdiv * (1 << outdiv)); in ar934x_ddrpll_to_hz()
|
| /u-boot/arch/arm/mach-socfpga/ |
| A D | clock_manager_s10.c | 201 unsigned long fref, refdiv, mdiv, reg, vco; in cm_get_main_vco_clk_hz() local
219 refdiv = (reg >> CLKMGR_PLLGLOB_REFCLKDIV_OFFSET) & in cm_get_main_vco_clk_hz()
225 vco = fref / refdiv; in cm_get_main_vco_clk_hz()
232 unsigned long fref, refdiv, mdiv, reg, vco; in cm_get_per_vco_clk_hz() local
250 refdiv = (reg >> CLKMGR_PLLGLOB_REFCLKDIV_OFFSET) & in cm_get_per_vco_clk_hz()
256 vco = fref / refdiv; in cm_get_per_vco_clk_hz()
|
| /u-boot/arch/arm/include/asm/arch-rockchip/ |
| A D | clock.h | 58 .refdiv = _refdiv, \
73 unsigned int refdiv; member
|
| A D | cru_rk3036.h | 59 u32 refdiv; member
|
| A D | cru_rk3128.h | 66 u32 refdiv; member
|
| A D | cru_rk322x.h | 60 u32 refdiv; member
|
| A D | cru_rv1108.h | 56 u32 refdiv; member
|
| A D | cru_px30.h | 104 unsigned int refdiv; member
|
| /u-boot/arch/m68k/cpu/mcf532x/ |
| A D | speed.c | 70 u32 refdiv = (1 << ((in_be32(&pll->pcr) & PLL_PCR_REFDIV(7)) >> 8)); in get_sys_clock() local
73 return (((FREF * pfdr) / refdiv) / busdiv); in get_sys_clock()
|
| /u-boot/arch/mips/mach-ath79/ar933x/ |
| A D | lowlevel_init.S | 19 #define MK_PLL_CONF(divint, refdiv, range, outdiv) \ argument
21 ((0x1F & refdiv) << 16) | \
|
| /u-boot/arch/mips/mach-ath79/qca953x/ |
| A D | lowlevel_init.S | 14 #define MK_PLL_CONF(divint, refdiv, range, outdiv) \ argument
16 ((0x1F & refdiv) << 16) | \
|
| /u-boot/drivers/ram/rockchip/ |
| A D | sdram_rk3328.c | 78 unsigned int refdiv, postdiv1, postdiv2, fbdiv; in rkclk_set_dpll() local
82 refdiv = 1; in rkclk_set_dpll()
102 fbdiv = (mhz * refdiv * postdiv1 * postdiv2) / 24; in rkclk_set_dpll()
106 writel(DSMPD(1) | POSTDIV2(postdiv2) | REFDIV(refdiv), in rkclk_set_dpll()
|
| A D | sdram_px30.c | 156 unsigned int refdiv, postdiv1, postdiv2, fbdiv; in rkclk_set_dpll() local
160 refdiv = 1; in rkclk_set_dpll()
180 fbdiv = (mhz * refdiv * postdiv1 * postdiv2) / 24; in rkclk_set_dpll()
185 writel(DSMPD(1) | POSTDIV2(postdiv2) | REFDIV(refdiv), in rkclk_set_dpll()
|
| /u-boot/arch/arm/mach-rockchip/rk3036/ |
| A D | sdram_rk3036.c | 345 dpll_init_cfg.refdiv << PLL_REFDIV_SHIFT)); in rkdclk_init()
|