| /u-boot/arch/arm/mach-lpc32xx/ |
| A D | dram.c | 33 writel(0x7FF, &emc->refresh); in ddr_init()
53 writel((((ck / dram->refresh) >> 4) & 0x7FF), &emc->refresh); in ddr_init()
61 writel((((128) >> 4) & 0x7FF), &emc->refresh); in ddr_init()
64 writel((((ck / dram->refresh) >> 4) & 0x7FF), &emc->refresh); in ddr_init()
|
| /u-boot/board/work-microwave/work_92105/ |
| A D | work_92105_spl.c | 33 .refresh = 128000,
53 .refresh = 128000,
|
| /u-boot/drivers/video/ |
| A D | videomodes.c | 203 GET_OPTION ("refresh:", pPar->refresh) in video_get_params()
299 unsigned int i, xres, yres, depth, refresh; in video_get_ctfb_res_modes() local
305 if (!video_get_video_mode(&xres, &yres, &depth, &refresh, options)) in video_get_ctfb_res_modes()
311 res_mode_init[i].refresh == refresh) { in video_get_ctfb_res_modes()
319 xres, yres, depth, refresh, (*mode_ret)->xres, in video_get_ctfb_res_modes()
320 (*mode_ret)->yres, *depth_ret, (*mode_ret)->refresh); in video_get_ctfb_res_modes()
411 mode->refresh = EDID_DETAILED_TIMING_PIXEL_CLOCK(*t) / in video_edid_dtd_to_ctfb_res_modes()
|
| A D | fsl_diu_fb.c | 23 .refresh = 60,
40 .refresh = 60,
62 .refresh = 60,
78 .refresh = 60,
94 .refresh = 60,
110 .refresh = 60,
|
| A D | videomodes.h | 38 int refresh; /* vertical refresh rate in hz */ member
|
| A D | fsl_dcu_fb.c | 95 .refresh = 60,
114 .refresh = 60,
130 .refresh = 60,
146 .refresh = 60,
162 .refresh = 60,
|
| /u-boot/board/freescale/mx51evk/ |
| A D | mx51evk_video.c | 21 .refresh = 57,
37 .refresh = 60,
|
| /u-boot/board/freescale/mx53loco/ |
| A D | mx53loco_video.c | 19 .refresh = 57,
35 .refresh = 60,
|
| /u-boot/arch/arm/include/asm/arch-mx35/ |
| A D | sys_proto.h | 13 u32 col, u32 dsize, u32 refresh);
|
| /u-boot/board/boundary/nitrogen6x/ |
| A D | nitrogen6x.c | 468 .refresh = 60,
488 .refresh = 60,
508 .refresh = 60,
528 .refresh = 60,
548 .refresh = 60,
568 .refresh = 60,
588 .refresh = 60,
608 .refresh = 60,
628 .refresh = 60,
648 .refresh = 57,
[all …]
|
| /u-boot/arch/arm/include/asm/arch-lpc32xx/ |
| A D | emc.h | 18 u32 refresh; /* Configures dyn memory refresh operation */ member
94 u32 refresh; member
|
| /u-boot/arch/arm/cpu/arm1136/mx35/ |
| A D | mx35_sdram.c | 40 u32 row, u32 col, u32 dsize, u32 refresh) in mx3_setup_sdram_bank() argument
114 writel(set_mode(ctlval, 1, SMODE_NORMAL) | refresh, in mx3_setup_sdram_bank()
|
| /u-boot/doc/device-tree-bindings/clock/ |
| A D | rockchip,rk3288-dmc.txt | 23 …ck frequency high than sr-enable-freq,this driver should enable the automatic self refresh function
25 …refresh-cnt: Self Refresh idle period. Memories are placed into Self-Refresh mode if the NIF is id…
139 rockchip,auto-self-refresh-cnt = <0>;
|
| /u-boot/drivers/video/tegra124/ |
| A D | display.c | 31 int h_total, v_total, refresh; in tegra_dc_calc_refresh() local
40 refresh = pclk / h_total; in tegra_dc_calc_refresh()
41 refresh *= 1000; in tegra_dc_calc_refresh()
42 refresh /= v_total; in tegra_dc_calc_refresh()
44 return refresh; in tegra_dc_calc_refresh()
49 int refresh = tegra_dc_calc_refresh(timing); in print_mode() local
52 timing->hactive.typ, timing->vactive.typ, refresh / 1000, in print_mode()
53 refresh % 1000, timing->pixelclock.typ); in print_mode()
|
| /u-boot/board/timll/devkit3250/ |
| A D | devkit3250_spl.c | 41 .refresh = 130000, /* 800 clock cycles */
|
| /u-boot/board/beckhoff/mx53cx9020/ |
| A D | mx53cx9020_video.c | 25 .refresh = 60,
|
| /u-boot/include/ |
| A D | spd.h | 27 unsigned char refresh; /* 12 Refresh Rate/Type */ member
|
| /u-boot/board/ge/mx53ppd/ |
| A D | mx53ppd_video.c | 78 .refresh = 60,
|
| /u-boot/board/technexion/pico-imx6/ |
| A D | pico-imx6.c | 181 .refresh = 60,
201 .refresh = 60,
221 .refresh = 60,
|
| /u-boot/board/Seagate/nas220/ |
| A D | kwbimage.cfg | 28 # bit13-0: 0xa00 (2560 DDR2 clks refresh rate)
30 # bit24: 1= enable exit self refresh mode on DDR access
37 # bit 5: 0=clk is driven during self refresh, we don't care for APX
|
| /u-boot/board/Marvell/sheevaplug/ |
| A D | kwbimage.cfg | 23 # bit13-0: 0xc30 (3120 DDR2 clks refresh rate)
25 # bit24: 1= enable exit self refresh mode on DDR access
32 # bit 5: 0=clk is driven during self refresh, we don't care for APX
|
| /u-boot/board/Seagate/dockstar/ |
| A D | kwbimage.cfg | 26 # bit13-0: 0xc30 (3120 DDR2 clks refresh rate)
28 # bit24: 1= enable exit self refresh mode on DDR access
35 # bit 5: 0=clk is driven during self refresh, we don't care for APX
|
| /u-boot/board/Seagate/goflexhome/ |
| A D | kwbimage.cfg | 29 # bit13-0: 0xc30 (3120 DDR2 clks refresh rate)
31 # bit24: 1= enable exit self refresh mode on DDR access
38 # bit 5: 0=clk is driven during self refresh, we don't care for APX
|
| /u-boot/board/Synology/ds109/ |
| A D | kwbimage.cfg | 27 # bit13-0: 0xc30 (3120 DDR2 clks refresh rate)
29 # bit24: 1= enable exit self refresh mode on DDR access
36 # bit 5: 0=clk is driven during self refresh, we don't care for APX
|
| /u-boot/board/Marvell/dreamplug/ |
| A D | kwbimage.cfg | 24 # bit13-0: 0xc30 (3120 DDR2 clks refresh rate)
26 # bit24: 1= enable exit self refresh mode on DDR access
33 # bit 5: 0=clk is driven during self refresh, we don't care for APX
|