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/u-boot/arch/arm/mach-socfpga/
A Dclock_manager_gen5.c31 static int cm_write_with_phase(u32 value, const void *reg_address, u32 mask) in cm_write_with_phase() argument
36 ret = wait_for_bit_le32(reg_address, mask, false, 20000, false); in cm_write_with_phase()
40 writel(value, reg_address); in cm_write_with_phase()
42 return wait_for_bit_le32(reg_address, mask, false, 20000, false); in cm_write_with_phase()

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