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Searched refs:reg_ctrl (Results 1 – 5 of 5) sorted by relevance

/u-boot/drivers/spi/
A Dmxc_spi.c235 s32 reg_ctrl, reg_config; in spi_cfg_mxc() local
247 reg_ctrl = MXC_CSPICTRL_MODE_MASK; in spi_cfg_mxc()
248 reg_write(&regs->ctrl, reg_ctrl); in spi_cfg_mxc()
249 reg_ctrl |= MXC_CSPICTRL_EN; in spi_cfg_mxc()
250 reg_write(&regs->ctrl, reg_ctrl); in spi_cfg_mxc()
270 reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_SELCHAN(3)) | in spi_cfg_mxc()
272 reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_PREDIV(0x0F)) | in spi_cfg_mxc()
274 reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_POSTDIV(0x0F)) | in spi_cfg_mxc()
303 debug("reg_ctrl = 0x%x\n", reg_ctrl); in spi_cfg_mxc()
304 reg_write(&regs->ctrl, reg_ctrl); in spi_cfg_mxc()
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/u-boot/arch/arm/include/asm/arch-sunxi/
A Ddisplay.h139 u32 reg_ctrl; /* 0x870 */ member
/u-boot/arch/arm/mach-imx/mx6/
A Dddr.c63 static void modify_dg_result(u32 *reg_st0, u32 *reg_st1, u32 *reg_ctrl) in modify_dg_result() argument
72 val_ctrl = readl(reg_ctrl); in modify_dg_result()
87 writel(val_ctrl, reg_ctrl); in modify_dg_result()
/u-boot/drivers/net/
A De1000.c1723 uint32_t reg_ctrl, reg_ctrl_ext; in e1000_initialize_hardware_bits() local
1773 reg_ctrl = E1000_READ_REG(hw, CTRL); in e1000_initialize_hardware_bits()
1774 reg_ctrl &= ~(1 << 29); in e1000_initialize_hardware_bits()
1777 E1000_WRITE_REG(hw, CTRL, reg_ctrl); in e1000_initialize_hardware_bits()
/u-boot/drivers/video/sunxi/
A Dsunxi_display.c521 setbits_le32(&de_be->reg_ctrl, SUNXI_DE_BE_REG_CTRL_LOAD_REGS); in sunxi_composer_enable()

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