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Searched refs:reg_mask (Results 1 – 8 of 8) sorted by relevance

/u-boot/drivers/net/
A Dmdio_mux_i2creg.c52 u32 reg_mask[2]; in mdio_mux_i2creg_probe() local
57 err = dev_read_u32_array(dev, "mux-reg-masks", reg_mask, 2); in mdio_mux_i2creg_probe()
88 priv->reg = (int)reg_mask[0]; in mdio_mux_i2creg_probe()
89 priv->mask = (int)reg_mask[1]; in mdio_mux_i2creg_probe()
/u-boot/drivers/pinctrl/mvebu/
A Dpinctrl-armada-37xx.c74 u32 reg_mask; member
111 .reg_mask = _mask, \
121 .reg_mask = _mask, \
131 .reg_mask = _mask, \
141 .reg_mask = _mask, \
152 .reg_mask = _mask, \
278 unsigned int mask = grp->reg_mask; in armada_37xx_pmx_set_by_name()
/u-boot/drivers/memory/
A Dstm32-fmc2-ebi.c166 u32 reg_mask; member
333 clrsetbits_le32(ebi->io_base + reg, prop->reg_mask, in stm32_fmc2_ebi_set_bit_field()
334 setup ? prop->reg_mask : 0); in stm32_fmc2_ebi_set_bit_field()
704 .reg_mask = FMC2_BCR1_CCLKEN,
712 .reg_mask = FMC2_BCR_MUXEN,
725 .reg_mask = FMC2_BCR_WAITPOL,
732 .reg_mask = FMC2_BCR_WAITCFG,
740 .reg_mask = FMC2_BCR_WAITEN,
748 .reg_mask = FMC2_BCR_ASYNCWAIT,
/u-boot/drivers/ddr/marvell/a38x/
A Dddr3_training_ip_def.h159 unsigned int reg_mask; member
A Dddr3_training_ip_flow.h78 u32 reg_addr, u32 data_value, u32 reg_mask);
A Dddr3_init.h153 int ddr3_tip_reg_read(u32 dev_num, u32 reg_addr, u32 *data, u32 reg_mask);
A Dddr3_training_leveling.c1690 u32 reg_val, reg_mask; in mv_ddr_rl_dqs_burst() local
1698 reg_mask = (TRAINING_ECC_MUX_MASK << TRAINING_ECC_MUX_OFFS) | in mv_ddr_rl_dqs_burst()
1700 reg_val &= ~reg_mask; in mv_ddr_rl_dqs_burst()
1707 reg_mask = (TRN_START_MASK << TRN_START_OFFS); in mv_ddr_rl_dqs_burst()
1708 reg_val &= ~reg_mask; in mv_ddr_rl_dqs_burst()
A Dddr3_training.c1095 u32 data_value, u32 reg_mask) in ddr3_tip_bus_read_modify_write() argument
1113 data_value = (data_val & (~reg_mask)) | (data_value & reg_mask); in ddr3_tip_bus_read_modify_write()
1975 odpg_default_value[index_cnt].reg_mask)); in ddr3_tip_restore_dunit_regs()

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