Searched refs:reg_val1 (Results 1 – 2 of 2) sorted by relevance
| /u-boot/drivers/net/phy/ |
| A D | aquantia.c | 411 u32 reg_val1 = 0; in aquantia_config() local
452 reg_val1 = phy_read(phydev, MDIO_MMD_PHYXS, in aquantia_config()
454 if ((reg_val1 & AQUANTIA_SI_IN_USE_MASK) == AQUANTIA_SI_USXGMII) in aquantia_config()
509 reg_val1 = phy_read(phydev, MDIO_MMD_PHYXS, in aquantia_config()
513 reg_val1 |= AQUANTIA_USX_AUTONEG_CONTROL_ENA; in aquantia_config()
517 reg_val1 &= ~AQUANTIA_USX_AUTONEG_CONTROL_ENA; in aquantia_config()
523 AQUANTIA_VENDOR_PROVISIONING_REG, reg_val1); in aquantia_config()
544 reg_val1 = phy_read(phydev, MDIO_MMD_VEND1, AQUANTIA_FIRMWARE_ID); in aquantia_config()
548 (reg_val1 & AQUANTIA_FIRMWARE_MAJOR_MASK) >> 8, in aquantia_config()
549 reg_val1 & AQUANTIA_FIRMWARE_MINOR_MASK, in aquantia_config()
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| /u-boot/drivers/ddr/marvell/a38x/ |
| A D | ddr3_training.c | 1981 int ddr3_tip_adll_regs_bypass(u32 dev_num, u32 reg_val1, u32 reg_val2) in ddr3_tip_adll_regs_bypass() argument
1994 CTX_PHY_REG(effective_cs), reg_val1)); in ddr3_tip_adll_regs_bypass()
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