Home
last modified time | relevance | path

Searched refs:reg_write (Results 1 – 23 of 23) sorted by relevance

/u-boot/board/Synology/ds414/
A Dds414.c136 reg_write(GPP_DATA_OUT_REG(0), DS414_GPP_OUT_VAL_LOW); in board_early_init_f()
137 reg_write(GPP_DATA_OUT_REG(1), DS414_GPP_OUT_VAL_MID); in board_early_init_f()
138 reg_write(GPP_DATA_OUT_REG(2), DS414_GPP_OUT_VAL_HIGH); in board_early_init_f()
141 reg_write(GPP_DATA_IN_POL_REG(0), DS414_GPP_OUT_POL_LOW); in board_early_init_f()
142 reg_write(GPP_DATA_IN_POL_REG(1), DS414_GPP_OUT_POL_MID); in board_early_init_f()
143 reg_write(GPP_DATA_IN_POL_REG(2), DS414_GPP_OUT_POL_HIGH); in board_early_init_f()
146 reg_write(GPP_DATA_OUT_EN_REG(0), DS414_GPP_OUT_ENA_LOW); in board_early_init_f()
147 reg_write(GPP_DATA_OUT_EN_REG(1), DS414_GPP_OUT_ENA_MID); in board_early_init_f()
148 reg_write(GPP_DATA_OUT_EN_REG(2), DS414_GPP_OUT_ENA_HIGH); in board_early_init_f()
151 reg_write(MPP_CONTROL_REG(i), ds414_mpp_control[i]); in board_early_init_f()
[all …]
A Dcmd_syno.c194 reg_write(POWER_MNG_CTRL_REG, pwr_mng_ctrl_reg); in do_syno_clk_gate()
/u-boot/arch/arm/mach-mvebu/serdes/axp/
A Dhigh_speed_env_lib.c644 reg_write(SOC_CTRL_REG, tmp); in serdes_phy_config()
1074 reg_write(PEX_PHY_ACCESS_REG in serdes_phy_config()
1104 reg_write(SATA_BASE_REG in serdes_phy_config()
1113 reg_write(SATA_BASE_REG in serdes_phy_config()
1145 reg_write(MV_ETH_REGS_BASE in serdes_phy_config()
1154 reg_write(MV_ETH_REGS_BASE in serdes_phy_config()
1168 reg_write in serdes_phy_config()
1175 reg_write in serdes_phy_config()
1202 reg_write(SOC_CTRL_REG, tmp); in serdes_phy_config()
1335 reg_write in serdes_phy_config()
[all …]
/u-boot/drivers/ddr/marvell/axp/
A Dxor.c42 reg_write(XOR_WINDOW_CTRL_REG(0, 0), reg); in mv_sys_xor_init()
46 reg_write(XOR_BASE_ADDR_REG(0, dram_info->num_cs), base); in mv_sys_xor_init()
48 reg_write(XOR_SIZE_MASK_REG(0, dram_info->num_cs), 0x03FF0000); in mv_sys_xor_init()
72 reg_write(XOR_BASE_ADDR_REG(0, cs_count), base); in mv_sys_xor_init()
75 reg_write(XOR_SIZE_MASK_REG(0, cs_count), 0x0FFF0000); in mv_sys_xor_init()
89 reg_write(XOR_WINDOW_CTRL_REG(0, 0), xor_regs_ctrl_backup); in mv_sys_xor_finish()
91 reg_write(XOR_BASE_ADDR_REG(0, ui), xor_regs_base_backup[ui]); in mv_sys_xor_finish()
93 reg_write(XOR_SIZE_MASK_REG(0, ui), xor_regs_mask_backup[ui]); in mv_sys_xor_finish()
95 reg_write(XOR_ADDR_OVRD_REG(0, 0), 0); in mv_sys_xor_finish()
187 reg_write(XOR_BLOCK_SIZE_REG(XOR_UNIT(chan), XOR_CHAN(chan)), in mv_xor_mem_init()
[all …]
A Dddr3_write_leveling.c80 reg_write(REG_DUNIT_CTRL_LOW_ADDR, in ddr3_write_leveling_hw()
503 reg_write(REG_DUNIT_CTRL_LOW_ADDR, in ddr3_write_leveling_hw_reg_dimm()
674 reg_write(REG_DUNIT_CTRL_LOW_ADDR, in ddr3_write_leveling_sw()
688 reg_write(REG_DDR3_MR1_ADDR, reg); in ddr3_write_leveling_sw()
808 reg_write(REG_DDR3_MR1_ADDR, reg); in ddr3_write_leveling_sw()
846 reg_write(REG_DDR3_MR1_ADDR, reg); in ddr3_write_leveling_sw()
898 reg_write(REG_DUNIT_CTRL_LOW_ADDR, in ddr3_write_leveling_sw_reg_dimm()
923 reg_write(REG_DDR3_MR1_ADDR, reg); in ddr3_write_leveling_sw_reg_dimm()
996 reg_write(REG_DDR3_MR1_ADDR, reg); in ddr3_write_leveling_sw_reg_dimm()
1040 reg_write(REG_DDR3_MR1_ADDR, reg); in ddr3_write_leveling_sw_reg_dimm()
[all …]
A Dddr3_init.c167 reg_write(0x8c04, 0x40000000); in ddr3_restore_and_set_final_windows()
207 reg_write(0x8c04, 0); in ddr3_save_and_set_training_windows()
224 reg_write(REG_XBAR_WIN_19_CTRL_ADDR, 0); in ddr3_save_and_set_training_windows()
259 reg_write(win_remap_reg + in ddr3_save_and_set_training_windows()
473 reg_write(REG_SDRAM_CONFIG_ADDR, reg); in ddr3_init_main()
530 reg_write(REG_DRAM_AXI_CTRL_ADDR, 0); in ddr3_init_main()
558 reg_write(DLB_EVICTION_CONTROL_REG, 0x0); in ddr3_init_main()
643 reg_write(REG_SDRAM_CONFIG_ADDR, reg); in ddr3_init_main()
653 reg_write(REG_BOOTROM_ROUTINE_ADDR, in ddr3_init_main()
789 reg_write(ddr_mode->vals[j].reg_addr, in ddr3_static_training_init()
[all …]
A Dddr3_spd.c776 reg_write(REG_SDRAM_CONFIG_ADDR, reg);
952 reg_write(REG_DDR_CONT_HIGH_ADDR, reg);
959 reg_write(0x142C, reg);
1064 reg_write(REG_DDR3_MR0_CS_ADDR +
1077 reg_write(REG_DDR3_MR1_CS_ADDR +
1115 reg_write(REG_DDR3_MR2_CS_ADDR +
1124 reg_write(REG_DDR3_MR3_CS_ADDR +
1136 reg_write(REG_ODT_TIME_LOW_ADDR, reg);
1142 reg_write(REG_ODT_TIME_HIGH_ADDR, reg);
1171 reg_write(REG_ZQC_CONF_ADDR, reg);
[all …]
A Dddr3_hw_training.c111 reg_write(REG_SDRAM_CONFIG_ADDR, reg); in ddr3_hw_training()
543 reg_write(REG_SDRAM_TIMING_HIGH_ADDR, reg); in ddr3_set_performance_params()
631 reg_write(REG_DRAM_TRAINING_2_ADDR, reg); in ddr3_load_patterns()
648 reg_write(REG_DRAM_TRAINING_2_ADDR, reg); in ddr3_load_patterns()
652 reg_write(REG_DRAM_TRAINING_1_ADDR, reg); in ddr3_load_patterns()
656 reg_write(REG_DRAM_TRAINING_PATTERN_BASE_ADDR, 0); in ddr3_load_patterns()
661 reg_write(REG_DRAM_TRAINING_PATTERN_BASE_ADDR, in ddr3_load_patterns()
676 reg_write(REG_DRAM_TRAINING_ADDR, reg); in ddr3_load_patterns()
937 reg_write(REG_DRAM_TRAINING_2_ADDR, reg); in ddr3_training_suspend_resume()
1082 reg_write(REG_DUNIT_ODT_CTRL_ADDR, reg); in ddr3_odt_activate()
[all …]
A Dddr3_read_leveling.c81 reg_write(REG_DRAM_TRAINING_SHADOW_ADDR, reg); in ddr3_read_leveling_hw()
194 reg_write(REG_DRAM_TRAINING_2_ADDR, reg); in ddr3_read_leveling_sw()
212 reg_write(REG_DRAM_TRAINING_2_ADDR, reg); in ddr3_read_leveling_sw()
302 reg_write(REG_DRAM_TRAINING_2_ADDR, reg); in ddr3_read_leveling_sw()
312 reg_write(REG_DRAM_TRAINING_2_ADDR, reg); in ddr3_read_leveling_sw()
325 reg_write(REG_DRAM_TRAINING_2_ADDR, reg); in ddr3_read_leveling_sw()
449 reg_write(REG_DRAM_TRAINING_2_ADDR, reg); in ddr3_read_leveling_single_cs_rl_mode()
624 reg_write(REG_READ_DATA_SAMPLE_DELAYS_ADDR, in ddr3_read_leveling_single_cs_rl_mode()
727 reg_write(REG_READ_DATA_READY_DELAYS_ADDR, reg); in ddr3_read_leveling_single_cs_rl_mode()
803 reg_write(REG_DRAM_TRAINING_2_ADDR, reg); in ddr3_read_leveling_single_cs_window_mode()
[all …]
A Dddr3_pbs.c113 reg_write(REG_DRAM_TRAINING_2_ADDR, reg); in ddr3_pbs_tx()
164 reg_write(REG_DRAM_TRAINING_2_ADDR, reg); in ddr3_pbs_tx()
288 reg_write(REG_DRAM_TRAINING_2_ADDR, reg); in ddr3_pbs_tx()
385 reg_write(REG_DRAM_TRAINING_2_ADDR, reg); in ddr3_pbs_tx()
389 reg_write(REG_DRAM_TRAINING_1_ADDR, reg); in ddr3_pbs_tx()
556 reg_write(REG_DRAM_TRAINING_2_ADDR, reg); in ddr3_pbs_rx()
606 reg_write(REG_DRAM_TRAINING_2_ADDR, reg); in ddr3_pbs_rx()
678 reg_write(REG_DRAM_TRAINING_ADDR, reg); in ddr3_pbs_rx()
696 reg_write(REG_DRAM_TRAINING_ADDR, reg); in ddr3_pbs_rx()
897 reg_write(REG_DRAM_TRAINING_2_ADDR, reg); in ddr3_pbs_rx()
[all …]
A Dddr3_dqs.c144 reg_write(REG_DRAM_TRAINING_2_ADDR, reg); in ddr3_dqs_centralization_rx()
148 reg_write(REG_DRAM_TRAINING_ADDR, reg); /* 0x15B0 - Training Register */ in ddr3_dqs_centralization_rx()
163 reg_write(REG_DRAM_TRAINING_2_ADDR, reg); in ddr3_dqs_centralization_rx()
190 reg_write(REG_DRAM_TRAINING_2_ADDR, reg); in ddr3_dqs_centralization_rx()
197 reg_write(REG_DRAM_TRAINING_2_ADDR, reg); in ddr3_dqs_centralization_rx()
201 reg_write(REG_DRAM_TRAINING_1_ADDR, reg); in ddr3_dqs_centralization_rx()
226 reg_write(REG_DRAM_TRAINING_2_ADDR, reg); in ddr3_dqs_centralization_tx()
243 reg_write(REG_DRAM_TRAINING_2_ADDR, reg); in ddr3_dqs_centralization_tx()
270 reg_write(REG_DRAM_TRAINING_2_ADDR, reg); in ddr3_dqs_centralization_tx()
277 reg_write(REG_DRAM_TRAINING_2_ADDR, reg); in ddr3_dqs_centralization_tx()
[all …]
A Dddr3_sdram.c70 reg_write(XOR_CAUSE_REG(XOR_UNIT(chan)), in xor_waiton_eng()
511 reg_write(XOR_ADDR_OVRD_REG(0, 0), in ddr3_dram_sram_burst()
518 reg_write(XOR_ADDR_OVRD_REG(0, 0), in ddr3_dram_sram_burst()
646 reg_write(REG_DRAM_TRAINING_ADDR, reg); in ddr3_reset_phy_read_fifo()
654 reg_write(REG_DRAM_TRAINING_2_ADDR, reg); in ddr3_reset_phy_read_fifo()
667 reg_write(REG_DRAM_TRAINING_ADDR, reg); in ddr3_reset_phy_read_fifo()
A Dddr3_init.h122 static inline void reg_write(u32 addr, u32 val) in reg_write() function
/u-boot/drivers/ddr/marvell/a38x/
A Dxor.c46 reg_write(XOR_WINDOW_CTRL_REG(0, 0), reg); in mv_sys_xor_init()
81 reg_write(XOR_BASE_ADDR_REG(0, ui), (u32)base); in mv_sys_xor_init()
85 reg_write(XOR_SIZE_MASK_REG(0, ui), (u32)size_mask); in mv_sys_xor_init()
98 reg_write(XOR_WINDOW_CTRL_REG(0, 0), ui_xor_regs_ctrl_backup); in mv_sys_xor_finish()
100 reg_write(XOR_BASE_ADDR_REG(0, ui), in mv_sys_xor_finish()
103 reg_write(XOR_SIZE_MASK_REG(0, ui), in mv_sys_xor_finish()
106 reg_write(XOR_ADDR_OVRD_REG(0, 0), 0); in mv_sys_xor_finish()
188 reg_write(XOR_CONFIG_REG(XOR_UNIT(chan), XOR_CHAN(chan)), temp); in mv_xor_mem_init()
200 reg_write(XOR_BLOCK_SIZE_REG(XOR_UNIT(chan), XOR_CHAN(chan)), in mv_xor_mem_init()
207 reg_write(XOR_INIT_VAL_LOW_REG(XOR_UNIT(chan)), init_val_low); in mv_xor_mem_init()
[all …]
A Dmv_ddr_plat.c202 reg_write(TSEN_CONTROL_LSB_REG, reg); in ddr3_ctrl_get_junc_temp()
257 reg_write(addr, reg_val); in dunit_write()
376 reg_write(DUAL_DUNIT_CFG_REG, reg); in ddr3_tip_a38x_select_ddr_controller()
1154 reg_write(ADDRESS_FILTERING_END_REGISTER, 0); in ddr3_save_and_set_training_windows()
1161 reg_write(REG_XBAR_WIN_19_CTRL_ADDR, 0); in ddr3_save_and_set_training_windows()
1197 reg_write(win_remap_reg + in ddr3_save_and_set_training_windows()
1268 reg_write(TRAINING_DBG_3_REG, reg_val); in mv_ddr_pre_training_soc_config()
1276 reg_write(AXI_CTRL_REG, 0); in mv_ddr_pre_training_soc_config()
1294 reg_write(config_table_ptr[i].reg_addr, in ddr3_new_tip_dlb_config()
1314 reg_write(DLB_CTRL_REG, reg); in ddr3_new_tip_dlb_config()
[all …]
A Dmv_ddr_sys_env_lib.c71 reg_write(MPP_CONTROL_REG(MPP_REG_NUM(gpio)), reg); in mv_ddr_sys_env_suspend_wakeup_check()
76 reg_write(GPP_DATA_OUT_EN_REG(GPP_REG_NUM(gpio)), reg); in mv_ddr_sys_env_suspend_wakeup_check()
A Dddr_ml_wrapper.h126 static inline void reg_write(u32 addr, u32 val) in reg_write() function
/u-boot/arch/arm/mach-mvebu/serdes/a38x/
A Dsys_env_lib.c110 reg_write(MPP_CONTROL_REG(MPP_REG_NUM(gpio)), reg); in sys_env_suspend_wakeup_check()
115 reg_write(GPP_DATA_OUT_EN_REG(GPP_REG_NUM(gpio)), reg); in sys_env_suspend_wakeup_check()
253 reg_write(RTC_MEMORY_WRAPPER_REG(i), RTC_MEMORY_WRAPPER_CTRL_VAL); in mv_rtc_config()
260 reg_write(AVS_DEBUG_CNTR_REG, AVS_DEBUG_CNTR_DEFAULT_VALUE); in mv_avs_init()
261 reg_write(AVS_DEBUG_CNTR_REG, AVS_DEBUG_CNTR_DEFAULT_VALUE); in mv_avs_init()
275 reg_write(AVS_ENABLED_CONTROL, avs_reg_data); in mv_avs_init()
A Dctrl_pex.c49 reg_write(PEX_CAPABILITIES_REG(pex_idx), tmp); in hws_pex_config()
82 reg_write(SOC_CTRL_REG, tmp); in hws_pex_config()
178 reg_write(PEX_LINK_CTRL_STATUS2_REG(pex_idx), tmp); in hws_pex_config()
184 reg_write(PEX_CTRL_REG(pex_idx), tmp); in hws_pex_config()
221 reg_write(PEX_CFG_DIRECT_ACCESS in hws_pex_config()
245 reg_write(PEX_STATUS_REG(pex_if), pex_status); in pex_local_bus_num_set()
260 reg_write(PEX_STATUS_REG(pex_if), pex_status); in pex_local_dev_num_set()
336 reg_write(PEX_CFG_ADDR_REG(pex_if), pex_data); in pex_config_read()
A Dhigh_speed_env_spec.c1397 reg_write(CORE_PLL_PARAMETERS_REG, 0x42e9f003); in hws_pre_serdes_init_config()
1402 reg_write(CORE_PLL_CONFIG_REG, data); in hws_pre_serdes_init_config()
1460 reg_write(reg_addr, data); in serdes_polarity_config()
1724 reg_write(SOC_CONTROL_REG1, reg_data); in serdes_power_up_ctrl()
1734 reg_write(((PEX_IF_REGS_BASE(pex_idx)) + 0x6c), in serdes_power_up_ctrl()
1742 reg_write(((PEX_IF_REGS_BASE(pex_idx)) + 0x6c), in serdes_power_up_ctrl()
1861 reg_write(GBE_CONFIGURATION_REG, reg_data); in serdes_power_up_ctrl()
2000 reg_write(COMMON_PHYS_SELECTORS_REG, reg_data); in hws_update_serdes_phy_selectors()
2090 reg_write(POWER_AND_PLL_CTRL_REG + in hws_ref_clock_set()
2099 reg_write(GLOBAL_PM_CTRL + in hws_ref_clock_set()
[all …]
A Dseq_exec.c61 reg_write(reg_addr, reg_data); in write_op_execute()
/u-boot/arch/arm/mach-mvebu/
A Ddram.c135 reg_write(XOR_WINDOW_CTRL_REG(SCRB_XOR_UNIT, SCRB_XOR_CHAN), reg); in mv_xor_init2()
142 reg_write(XOR_BASE_ADDR_REG(SCRB_XOR_UNIT, SCRB_XOR_WIN), in mv_xor_init2()
148 reg_write(XOR_SIZE_MASK_REG(SCRB_XOR_UNIT, SCRB_XOR_WIN), size); in mv_xor_init2()
158 reg_write(XOR_WINDOW_CTRL_REG(SCRB_XOR_UNIT, SCRB_XOR_CHAN), in mv_xor_finish2()
160 reg_write(XOR_BASE_ADDR_REG(SCRB_XOR_UNIT, SCRB_XOR_WIN), in mv_xor_finish2()
162 reg_write(XOR_SIZE_MASK_REG(SCRB_XOR_UNIT, SCRB_XOR_WIN), in mv_xor_finish2()
182 reg_write(REG_SDRAM_CONFIG_ADDR, temp); in dram_ecc_scrubbing()
212 reg_write(REG_SDRAM_CONFIG_ADDR, temp); in dram_ecc_scrubbing()
/u-boot/drivers/spi/
A Dmxc_spi.c117 #define reg_write(a, v) writel(v, a) macro
248 reg_write(&regs->ctrl, reg_ctrl); in spi_cfg_mxc()
250 reg_write(&regs->ctrl, reg_ctrl); in spi_cfg_mxc()
304 reg_write(&regs->ctrl, reg_ctrl); in spi_cfg_mxc()
306 reg_write(&regs->cfg, reg_config); in spi_cfg_mxc()
313 reg_write(&regs->intr, 0); in spi_cfg_mxc()
338 reg_write(&regs->cfg, mxcs->cfg_reg); in spi_xchg_single()
359 reg_write(&regs->txdata, data); in spi_xchg_single()
380 reg_write(&regs->txdata, data); in spi_xchg_single()
483 reg_write(&regs->rxdata, 1); in mxc_spi_claim_bus_internal()
[all …]

Completed in 42 milliseconds