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/u-boot/drivers/reset/
A DMakefile6 obj-$(CONFIG_DM_RESET) += reset-uclass.o
7 obj-$(CONFIG_SANDBOX_MBOX) += sandbox-reset.o
9 obj-$(CONFIG_STI_RESET) += sti-reset.o
10 obj-$(CONFIG_STM32_RESET) += stm32-reset.o
13 obj-$(CONFIG_RESET_TI_SCI) += reset-ti-sci.o
14 obj-$(CONFIG_RESET_HSDK) += reset-hsdk.o
20 obj-$(CONFIG_RESET_MESON) += reset-meson.o
23 obj-$(CONFIG_RESET_MTMIPS) += reset-mtmips.o
24 obj-$(CONFIG_RESET_SUNXI) += reset-sunxi.o
26 obj-$(CONFIG_RESET_IMX7) += reset-imx7.o
[all …]
A DKconfig4 bool "Enable reset controllers using Driver Model"
9 reset controller hardware module within the chip. In U-Boot, reset
16 bool "Enable the sandbox reset test driver"
24 bool "Enable the STi reset"
32 bool "Enable the STM32 reset"
39 bool "Enable Tegra CAR-based reset driver"
64 Support reset controller on BCM6345.
99 though is that some reset signals, like I2C or MISC reset multiple
174 U-Boot's reset framework to reset these hardware blocks.
191 initialization routines as reset lines.
[all …]
A Dreset-sunxi.c54 const struct ccu_reset *reset = priv_to_reset(priv, reset_ctl->id); in sunxi_set_reset() local
57 if (!(reset->flags & CCU_RST_F_IS_VALID)) { in sunxi_set_reset()
63 reset_ctl->id, reset->off, ilog2(reset->bit)); in sunxi_set_reset()
65 reg = readl(priv->base + reset->off); in sunxi_set_reset()
67 reg |= reset->bit; in sunxi_set_reset()
69 reg &= ~reset->bit; in sunxi_set_reset()
71 writel(reg, priv->base + reset->off); in sunxi_set_reset()
/u-boot/drivers/net/octeontx/
A Dxcv.c27 union xcvx_reset reset; in xcv_init_hw() local
32 reset.s.dllrst = 0; in xcv_init_hw()
37 reset.s.clkrst = 0; in xcv_init_hw()
52 reset.s.comp = 1; in xcv_init_hw()
63 reset.s.enable = 1; in xcv_init_hw()
68 reset.s.clkrst = 1; in xcv_init_hw()
80 union xcvx_reset reset; in xcv_setup_link() local
103 reset.s.tx_dat_rst_n = 1; in xcv_setup_link()
104 reset.s.rx_dat_rst_n = 1; in xcv_setup_link()
109 reset.s.tx_pkt_rst_n = 1; in xcv_setup_link()
[all …]
/u-boot/doc/device-tree-bindings/reset/
A Dreset.txt10 reset consumer (the module being reset, or a module managing when a sub-
14 A reset signal is represented by the phandle of the provider, plus a reset
24 may be reset. Instead, reset signals should be represented in the DT node
35 #reset-cells: Number of cells in a reset specifier; Typically 0 for nodes
37 reset outputs.
41 rst: reset-controller {
42 #reset-cells = <1>;
55 reset-names: List of reset signal name strings sorted in the same order as
57 match reset signal names with reset specifiers.
63 reset-names = "reset";
[all …]
A Dsyscon-reset.txt1 Generic SYSCON mapped register reset driver
3 This is a generic reset driver using syscon to map the reset register.
4 The reset is generally performed with a write to the reset register
6 shifted by the reset specifier/
16 - compatible: should contain "syscon-reset"
17 - #reset-cells: must be 1
22 - mask: accept only the reset specifiers defined by the mask (32 bit)
23 - assert-high: Bit to write when asserting a reset. Defaults to 1.
29 reset-controller {
30 compatible = "syscon-reset";
[all …]
A Dti,sci-reset.txt13 The reset controller node represents the resets of various hardware modules
19 - compatible: Must be "ti,sci-reset"
20 - #reset-cells: Must be 2. Please see the reset consumer node below for
28 k3_reset: reset-controller {
29 compatible = "ti,sci-reset";
30 #reset-cells = <2>;
36 Each of the reset consumer nodes should have the following properties,
41 - resets: A phandle and reset specifier pair, one pair for each reset signal
43 should point to the TI SCI reset controller node, and the reset
45 the device ID. The second cell should contain the reset mask value
/u-boot/drivers/sysreset/
A DKconfig2 # System reset devices
5 menu "System reset device drivers"
8 bool "Enable support for system reset drivers"
11 Enable system reset drivers which can be used to reset the CPU or
20 Enable system reset drivers which can be used to reset the CPU or
29 Enable system reset drivers which can be used to reset the CPU or
37 bool "sysreset implementation of the reset command"
60 bool "Enable support for GPIO reset driver"
65 pin which triggers cpu reset.
68 bool "Enable support for Microblaze soft reset"
[all …]
/u-boot/doc/device-tree-bindings/exynos/
A Demmc-reset.txt1 * Samsung eMMC reset
7 - compatible: should be "samsung,emmc-reset"
8 - reset-gpio: gpio chip for eMMC reset.
12 emmc-reset {
13 compatible = "samsung,emmc-reset";
14 reset-gpio = <&gpk1 2 0>;
/u-boot/arch/arm/dts/
A Dast2500-u-boot.dtsi3 #include <dt-bindings/reset/ast2500-reset.h>
13 #reset-cells = <1>;
16 rst: reset-controller {
18 compatible = "aspeed,ast2500-reset";
19 #reset-cells = <1>;
27 #reset-cells = <1>;
41 #reset-cells = <1>;
49 #reset-cells = <1>;
A Dast2600-u-boot.dtsi3 #include <dt-bindings/reset/ast2600-reset.h>
13 #reset-cells = <1>;
17 rst: reset-controller {
19 compatible = "aspeed,ast2600-reset";
21 #reset-cells = <1>;
30 #reset-cells = <1>;
A Dqcom-ipq4019.dtsi14 #include <dt-bindings/reset/qcom,ipq4019-reset.h>
59 #reset-cells = <1>;
70 reset: gcc-reset@1800000 { label
71 compatible = "qcom,gcc-reset-ipq4019";
74 #reset-cells = <1>;
146 resets = <&reset USB3_UNIPHY_PHY_ARES>;
147 reset-names = "por_rst";
156 resets = <&reset USB3_HSPHY_POR_ARES>, <&reset USB3_HSPHY_S_ARES>;
157 reset-names = "por_rst", "srif_rst";
189 resets = <&reset USB2_HSPHY_POR_ARES>, <&reset USB2_HSPHY_S_ARES>;
[all …]
A Dtegra20.dtsi19 reset-names = "host1x";
32 reset-names = "mpe";
41 reset-names = "vi";
50 reset-names = "epp";
59 reset-names = "isp";
68 reset-names = "2d";
76 reset-names = "3d";
87 reset-names = "dc";
104 reset-names = "dc";
195 #reset-cells = <1>;
[all …]
/u-boot/doc/device-tree-bindings/gpu/
A Dnvidia,tegra20-host1x.txt15 See ../reset/reset.txt for details.
31 See ../reset/reset.txt for details.
44 See ../reset/reset.txt for details.
57 See ../reset/reset.txt for details.
70 See ../reset/reset.txt for details.
83 See ../reset/reset.txt for details.
100 See ../reset/reset.txt for details.
118 See ../reset/reset.txt for details.
149 See ../reset/reset.txt for details.
181 See ../reset/reset.txt for details.
[all …]
/u-boot/arch/arm/mach-omap2/omap3/
A Demac.c20 u32 reset; in cpu_eth_init() local
23 reset = readl(&am35x_scm_general_regs->ip_sw_reset); in cpu_eth_init()
24 reset &= ~CPGMACSS_SW_RST; in cpu_eth_init()
25 writel(reset, &am35x_scm_general_regs->ip_sw_reset); in cpu_eth_init()
/u-boot/doc/device-tree-bindings/phy/
A Dphy-stih407-usb.txt9 - resets : list of phandle and reset specifier pairs. There should be two entries, one
11 - reset-names : list of reset signal names. Should be "global" and "port"
12 See: Documentation/devicetree/bindings/reset/st,sti-powerdown.txt
13 See: Documentation/devicetree/bindings/reset/reset.txt
23 reset-names = "global", "port";
/u-boot/arch/arm/mach-socfpga/
A Dreset_manager_s10.c21 void socfpga_per_reset(u32 reset, int set) in socfpga_per_reset() argument
25 if (RSTMGR_BANK(reset) == 0) in socfpga_per_reset()
27 else if (RSTMGR_BANK(reset) == 1) in socfpga_per_reset()
29 else if (RSTMGR_BANK(reset) == 2) in socfpga_per_reset()
31 else if (RSTMGR_BANK(reset) == 3) in socfpga_per_reset()
38 1 << RSTMGR_RESET(reset)); in socfpga_per_reset()
41 1 << RSTMGR_RESET(reset)); in socfpga_per_reset()
/u-boot/doc/device-tree-bindings/i2c/
A Dgeneric-acpi.txt14 - reset-gpios : GPIO used to assert reset to the device
18 - reset-delay-ms : Delay after de-asserting reset, in ms
19 - reset-off-delay-ms : Delay after asserting reset (during power off)
37 reset-gpios = <&gpio_n GPIO_36 GPIO_ACTIVE_HIGH>;
38 reset-delay-ms = <20>;
/u-boot/drivers/mmc/
A Dmmc-pwrseq.c23 struct gpio_desc reset; in mmc_pwrseq_set_power() local
26 ret = gpio_request_by_name(dev, "reset-gpios", 0, &reset, GPIOD_IS_OUT); in mmc_pwrseq_set_power()
29 dm_gpio_set_value(&reset, 1); in mmc_pwrseq_set_power()
31 dm_gpio_set_value(&reset, 0); in mmc_pwrseq_set_power()
/u-boot/arch/x86/dts/
A Dreset.dtsi2 reset: reset { label
3 compatible = "x86,reset";
/u-boot/test/dm/
A Dsyscon-reset.c30 struct udevice *reset; in dm_test_syscon_reset() local
36 &reset)); in dm_test_syscon_reset()
43 ut_asserteq(-EINVAL, reset_get_by_name(reset, "no_mask", &rst)); in dm_test_syscon_reset()
44 ut_asserteq(-EINVAL, reset_get_by_name(reset, "out_of_range", &rst)); in dm_test_syscon_reset()
45 ut_assertok(reset_get_by_name(reset, "valid", &rst)); in dm_test_syscon_reset()
/u-boot/arch/arm/cpu/armv7m/
A Dstart.S9 .globl reset
10 .type reset, %function
11 reset: label
/u-boot/board/logicpd/am3517evm/
A Dam3517evm.c79 .reset = am35x_musb_reset,
120 u32 reset; in misc_init_r() local
127 reset = readl(AM3517_IP_SW_RESET); in misc_init_r()
128 reset &= (~CPGMACSS_SW_RST); in misc_init_r()
129 writel(reset, AM3517_IP_SW_RESET); in misc_init_r()
/u-boot/arch/mips/dts/
A Dmt7620.dtsi3 #include <dt-bindings/reset/mt7620-reset.h>
44 #reset-cells = <1>;
51 reset-names = "sysreset";
64 reset-names = "uartf";
81 reset-names = "uartl";
158 reset-names = "wdt";
166 reset-names = "pio";
181 reset-names = "pio";
196 reset-names = "pio";
211 reset-names = "pio";
[all …]
/u-boot/doc/device-tree-bindings/net/
A Dstmmac.txt14 - snps,reset-gpio gpio number for phy reset.
15 - snps,reset-active-low boolean flag to indicate if phy reset is active low.
16 - snps,reset-delays-us is triplet of delays
17 The 1st cell is reset pre-delay in micro seconds.
18 The 2nd cell is reset pulse in micro seconds.
19 The 3rd cell is reset post-delay in micro seconds.
34 - resets: Should contain a phandle to the STMMAC reset signal, if any
35 - reset-names: Should contain the reset signal name "stmmaceth", if a
36 reset phandle is given

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