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Searched refs:rkclk_pll_get_rate (Results 1 – 8 of 8) sorted by relevance

/u-boot/drivers/clk/rockchip/
A Dclk_rv1108.c123 static uint32_t rkclk_pll_get_rate(struct rv1108_cru *cru, in rkclk_pll_get_rate() function
156 pll_rate = rkclk_pll_get_rate(cru, CLK_GENERAL); in rv1108_mac_set_clk()
158 pll_rate = rkclk_pll_get_rate(cru, CLK_ARM); in rv1108_mac_set_clk()
181 pll_rate = rkclk_pll_get_rate(cru, CLK_GENERAL); in rv1108_sfc_set_clk()
183 pll_rate = rkclk_pll_get_rate(cru, CLK_DDR); in rv1108_sfc_set_clk()
312 ulong parent_rate = rkclk_pll_get_rate(cru, CLK_GENERAL); in rv1108_aclk_bus_get_clk()
523 pll_rate = rkclk_pll_get_rate(cru, CLK_GENERAL); in rv1108_mmc_set_clk()
546 return rkclk_pll_get_rate(priv->cru, clk->id); in rv1108_clk_get_rate()
655 apll = rkclk_pll_get_rate(cru, CLK_ARM); in rkclk_init()
656 dpll = rkclk_pll_get_rate(cru, CLK_DDR); in rkclk_init()
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A Dclk_rk3368.c66 static uint32_t rkclk_pll_get_rate(struct rk3368_cru *cru, in rkclk_pll_get_rate() function
150 apllb = rkclk_pll_get_rate(cru, APLLB); in rkclk_init()
151 aplll = rkclk_pll_get_rate(cru, APLLL); in rkclk_init()
152 dpll = rkclk_pll_get_rate(cru, DPLL); in rkclk_init()
153 cpll = rkclk_pll_get_rate(cru, CPLL); in rkclk_init()
154 gpll = rkclk_pll_get_rate(cru, GPLL); in rkclk_init()
184 pll_rate = rkclk_pll_get_rate(cru, GPLL); in rk3368_mmc_get_clk()
190 pll_rate = rkclk_pll_get_rate(cru, CPLL); in rk3368_mmc_get_clk()
465 rate = rkclk_pll_get_rate(priv->cru, CPLL); in rk3368_clk_get_rate()
468 rate = rkclk_pll_get_rate(priv->cru, GPLL); in rk3368_clk_get_rate()
A Dclk_rk3036.c174 static uint32_t rkclk_pll_get_rate(struct rk3036_cru *cru, in rkclk_pll_get_rate() function
290 return rkclk_pll_get_rate(priv->cru, clk->id); in rk3036_clk_get_rate()
301 gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL); in rk3036_clk_set_rate()
A Dclk_rk322x.c176 static uint32_t rkclk_pll_get_rate(struct rk322x_cru *cru, in rkclk_pll_get_rate() function
360 gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL); in rk322x_clk_get_rate()
363 rate = rkclk_pll_get_rate(priv->cru, clk->id); in rk322x_clk_get_rate()
383 gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL); in rk322x_clk_set_rate()
A Dclk_rk3128.c242 static u32 rkclk_pll_get_rate(struct rk3128_cru *cru, in rkclk_pll_get_rate() function
477 parent = rkclk_pll_get_rate(cru, CLK_CODEC); in rk3128_vop_get_rate()
491 return rkclk_pll_get_rate(priv->cru, clk->id); in rk3128_clk_get_rate()
514 gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL); in rk3128_clk_set_rate()
A Dclk_rk3188.c230 static uint32_t rkclk_pll_get_rate(struct rk3188_cru *cru, in rkclk_pll_get_rate() function
468 gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL); in rk3188_clk_get_rate()
471 new_rate = rkclk_pll_get_rate(priv->cru, clk->id); in rk3188_clk_get_rate()
A Dclk_rk3288.c544 static uint32_t rkclk_pll_get_rate(struct rockchip_cru *cru, in rkclk_pll_get_rate() function
755 gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL); in rk3288_clk_get_rate()
758 new_rate = rkclk_pll_get_rate(priv->cru, clk->id); in rk3288_clk_get_rate()
798 gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL); in rk3288_clk_set_rate()
A Dclk_px30.c261 static uint32_t rkclk_pll_get_rate(struct px30_pll *pll, unsigned int *mode, in rkclk_pll_get_rate() function
757 parent = rkclk_pll_get_rate(&cru->pll[CPLL], &cru->mode, CPLL); in px30_vop_get_clk()
762 parent = rkclk_pll_get_rate(&cru->pll[NPLL], &cru->mode, NPLL); in px30_vop_get_clk()
1105 return rkclk_pll_get_rate(&cru->pll[pll_id], &cru->mode, pll_id); in px30_clk_get_pll_rate()
1115 return rkclk_pll_get_rate(&cru->pll[pll_id], &cru->mode, pll_id); in px30_clk_set_pll_rate()
1522 return rkclk_pll_get_rate(&pmucru->pll, &pmucru->pmu_mode, GPLL); in px30_pmuclk_get_gpll_rate()

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