| /u-boot/arch/x86/cpu/intel_common/ |
| A D | itss.c | 143 struct pmc_route *route; in route_pmc_gpio_gpe() local
146 for (i = 0, route = priv->route; i < priv->route_count; i++, route++) { in route_pmc_gpio_gpe()
147 if (pmc_gpe_num == route->pmc) in route_pmc_gpio_gpe()
148 return route->gpio; in route_pmc_gpio_gpe()
184 priv->route = (struct pmc_route *)dtplat->intel_pmc_routes; in itss_of_to_plat()
193 priv->route = malloc(size); in itss_of_to_plat()
194 if (!priv->route) in itss_of_to_plat()
196 ret = dev_read_u32_array(dev, "intel,pmc-routes", (u32 *)priv->route, in itss_of_to_plat()
|
| /u-boot/arch/x86/cpu/ivybridge/ |
| A D | lpc.c | 88 uint8_t route[8], *ptr; in pch_pirq_init() local
91 "intel,pirq-routing", route, sizeof(route))) in pch_pirq_init()
93 ptr = route; in pch_pirq_init()
113 u8 route[16]; in pch_gpi_routing() local
118 "intel,gpi-routing", route, sizeof(route))) in pch_gpi_routing()
121 for (reg = 0, gpi = 0; gpi < ARRAY_SIZE(route); gpi++) in pch_gpi_routing()
122 reg |= route[gpi] << (gpi * 2); in pch_gpi_routing()
|
| /u-boot/arch/x86/include/asm/ |
| A D | itss.h | 61 struct pmc_route *route; member
|
| A D | intel_pinctrl_defs.h | 143 #define PAD_IRQ_CFG(route, trig, inv) \ argument
144 (PAD_CFG0_ROUTE_##route | \
|
| /u-boot/arch/arm/mach-rockchip/px30/ |
| A D | Kconfig | 59 UART2 and UART3 can use two different set of pins to route the output.
60 For using the UART for early debugging the route to use needs
|
| /u-boot/drivers/video/bridge/ |
| A D | Kconfig | 17 LVDS capability, or where LVDS requires too many signals to route
27 or where LVDS requires too many signals to route on the PCB.
|
| /u-boot/doc/device-tree-bindings/gpio/ |
| A D | intel,x86-broadwell-pinctrl.txt | 24 - route - sets whether the pin is routed, either PIRQ_APIC_MASK or
61 route = <ROUTE_SCI>;
68 route = <ROUTE_SMI>;
147 <35 &gpio_acpi_smi 0>, /* pch_nmi_dbg_l (route in nmi_en) */
|
| /u-boot/arch/arm/mach-rockchip/rv1108/ |
| A D | Kconfig | 14 * one RS232 to USB port route to UART2 as debug port
|
| /u-boot/doc/device-tree-bindings/misc/ |
| A D | esm-k3.txt | 14 - ti,esm-pins : integer array of esm events IDs to route to external event
|
| /u-boot/drivers/pci_endpoint/ |
| A D | pcie-cadence.h | 190 #define CDNS_PCIE_NORMAL_MSG_ROUTING(route) \ argument
191 (((route) << 5) & CDNS_PCIE_NORMAL_MSG_ROUTING_MASK)
|
| /u-boot/arch/arm/include/asm/arch-sunxi/ |
| A D | display2.h | 42 u32 route; member
|
| /u-boot/drivers/usb/host/ |
| A D | xhci-mem.c | 735 int route = 0; in xhci_setup_addressable_virt_dev() local
767 route |= port_num << (hub->hub_depth * 4); in xhci_setup_addressable_virt_dev()
773 debug("route string %x\n", route); in xhci_setup_addressable_virt_dev()
775 slot_ctx->dev_info |= cpu_to_le32(route); in xhci_setup_addressable_virt_dev()
|
| /u-boot/doc/ |
| A D | README.fsl-hwconfig | 11 route either a 11.2896MHz or a 12.288MHz clock. The default is
|
| /u-boot/arch/x86/dts/ |
| A D | chromebook_samus.dts | 97 route = <ROUTE_SCI>;
105 route = <ROUTE_SMI>;
191 <35 &gpio_acpi_smi 0>, /* pch_nmi_dbg_l (route in nmi_en) */
|
| A D | chromebook_coral.dts | 303 * this route, i.e., if this route changes then the
|
| /u-boot/arch/arm/dts/ |
| A D | omap3-evm-processor-common.dtsi | 206 /* T2_GPIO_2 low to route GPIO_61 to on-board devices */
|
| /u-boot/drivers/video/sunxi/ |
| A D | sunxi_de2.c | 114 writel(1, &de_bld_regs->route); in sunxi_de2_mode_set()
|
| /u-boot/board/freescale/m5373evb/ |
| A D | README | 277 IP route cache hash table entries: 1024 (order: 0, 4096 bytes) TCP established hash table entries: …
315 route: SIOC[ADD|DEL]RT: No such process
|
| /u-boot/board/freescale/m54455evb/ |
| A D | README | 360 IP route cache hash table entries: 2048 (order: 0, 8192 bytes)
404 Adding static route for default gateway to 172.27.255.254:
|
| /u-boot/scripts/ |
| A D | get_maintainer.pl | 2492 my $route = "(?:\@$domain(?:,\@$rfc822_lwsp*$domain)*:$rfc822_lwsp*)";
2493 my $route_addr = "\\<$rfc822_lwsp*$route?$addr_spec\\>$rfc822_lwsp*";
|
| /u-boot/arch/arm/mach-rockchip/ |
| A D | Kconfig | 271 Rockchip SoCs have the ability to route the signals of the debug
|
| /u-boot/doc/driver-model/ |
| A D | usb-info.rst | 152 like. These are now implemented by the USB uclass and route through the
|