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Searched refs:rstctl (Results 1 – 8 of 8) sorted by relevance

/u-boot/arch/arm/cpu/armv8/fsl-layerscape/
A Dfsl_lsch2_serdes.c202 reg = in_be32(&serdes1_base->bank[i].rstctl); in setup_serdes_volt()
205 out_be32(&serdes1_base->bank[i].rstctl, reg); in setup_serdes_volt()
208 reg = in_be32(&serdes1_base->bank[i].rstctl); in setup_serdes_volt()
210 out_be32(&serdes1_base->bank[i].rstctl, reg); in setup_serdes_volt()
218 reg = in_be32(&serdes2_base->bank[i].rstctl); in setup_serdes_volt()
221 out_be32(&serdes2_base->bank[i].rstctl, reg); in setup_serdes_volt()
224 reg = in_be32(&serdes2_base->bank[i].rstctl); in setup_serdes_volt()
226 out_be32(&serdes2_base->bank[i].rstctl, reg); in setup_serdes_volt()
265 reg = in_be32(&serdes1_base->bank[i].rstctl); in setup_serdes_volt()
267 out_be32(&serdes1_base->bank[i].rstctl, reg); in setup_serdes_volt()
[all …]
A Dfsl_lsch3_serdes.c317 clrbits_le32(&serdes_base->bank[i].rstctl, in do_pll_reset()
321 setbits_le32(&serdes_base->bank[i].rstctl, in do_pll_reset()
353 setbits_le32(&serdes_base->bank[i].rstctl, in do_pll_reset_done()
365 setbits_le32(&serdes_base->bank[i].rstctl, RSTCTL_SDEN); in do_serdes_enable()
368 setbits_le32(&serdes_base->bank[i].rstctl, RSTCTL_PLLRST_B); in do_serdes_enable()
385 setbits_le32(&serdes_base->bank[i].rstctl, in do_pll_lock()
389 setbits_le32(&serdes_base->bank[i].rstctl, in do_pll_lock()
/u-boot/arch/powerpc/cpu/mpc85xx/
A Dfsl_corenet_serdes.c118 if (in_be32(&regs->bank[bank].rstctl) & SRDS_RSTCTL_SDPD) in serdes_lane_enabled()
471 u32 rstctl; in wait_for_rstdone() local
476 rstctl = in_be32(&srds_regs->bank[bank].rstctl); in wait_for_rstdone()
477 if (rstctl & SRDS_RSTCTL_RSTDONE) in wait_for_rstdone()
481 if (!(rstctl & SRDS_RSTCTL_RSTDONE)) in wait_for_rstdone()
607 setbits_be32(&srds2_regs->bank[0].rstctl, SRDS_RSTCTL_SDPD); in fsl_serdes_init()
648 setbits_be32(&srds_regs->bank[bank].rstctl, in fsl_serdes_init()
651 setbits_be32(&srds_regs->bank[bank].rstctl, in fsl_serdes_init()
867 setbits_be32(&srds_regs->bank[FSL_SRDS_BANK_2].rstctl, in fsl_serdes_init()
/u-boot/arch/powerpc/cpu/mpc8xxx/
A Dsrio.c95 if (in_be32((void *)&srds_regs->bank[0].rstctl) in srio_erratum_a004034()
/u-boot/arch/arm/include/asm/arch-ls102xa/
A Dimmap_ls102xa.h343 u32 rstctl; /* Reset Control Register */ member
/u-boot/arch/arm/include/asm/arch-fsl-layerscape/
A Dimmap_lsch3.h560 u32 rstctl; /* Reset Control Register */ member
A Dimmap_lsch2.h565 u32 rstctl; /* Reset Control Register */ member
/u-boot/arch/powerpc/include/asm/
A Dimmap_85xx.h2526 u32 rstctl; /* Reset Control Register */ member
2614 u32 rstctl; /* Reset Control Register */ member

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