| /u-boot/drivers/gpio/ |
| A D | tegra186_gpio.c | 47 uint32_t rval; in tegra186_gpio_set_out() local
50 rval = readl(reg); in tegra186_gpio_set_out()
55 writel(rval, reg); in tegra186_gpio_set_out()
58 rval = readl(reg); in tegra186_gpio_set_out()
64 writel(rval, reg); in tegra186_gpio_set_out()
72 uint32_t rval; in tegra186_gpio_set_val() local
75 rval = readl(reg); in tegra186_gpio_set_val()
80 writel(rval, reg); in tegra186_gpio_set_val()
104 uint32_t rval; in tegra186_gpio_get_value() local
116 return !!rval; in tegra186_gpio_get_value()
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| /u-boot/drivers/mtd/nand/raw/ |
| A D | nand_util.c | 483 int rval; in nand_verify_page_oob() local
497 if (!rval) in nand_verify_page_oob()
499 if (!rval) in nand_verify_page_oob()
523 int rval = 0; in nand_verify() local
536 if (!rval || (rval == -EUCLEAN)) in nand_verify()
539 if (rval) in nand_verify()
634 return rval; in nand_write_skip_bad()
711 int rval; in nand_read_skip_bad() local
744 if (!rval || rval == -EUCLEAN) in nand_read_skip_bad()
750 return rval; in nand_read_skip_bad()
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| /u-boot/arch/arm/mach-sunxi/ |
| A D | clock_sun4i.c | 201 uint32_t rval = readl(&ccm->pll3_cfg); in clock_get_pll3() local
202 int m = ((rval & CCM_PLL3_CTRL_M_MASK) >> CCM_PLL3_CTRL_M_SHIFT); in clock_get_pll3()
210 uint32_t rval = readl(&ccm->pll5_cfg); in clock_get_pll5p() local
211 int n = ((rval & CCM_PLL5_CTRL_N_MASK) >> CCM_PLL5_CTRL_N_SHIFT); in clock_get_pll5p()
212 int k = ((rval & CCM_PLL5_CTRL_K_MASK) >> CCM_PLL5_CTRL_K_SHIFT) + 1; in clock_get_pll5p()
213 int p = ((rval & CCM_PLL5_CTRL_P_MASK) >> CCM_PLL5_CTRL_P_SHIFT); in clock_get_pll5p()
221 uint32_t rval = readl(&ccm->pll6_cfg); in clock_get_pll6() local
222 int n = ((rval & CCM_PLL6_CTRL_N_MASK) >> CCM_PLL6_CTRL_N_SHIFT); in clock_get_pll6()
223 int k = ((rval & CCM_PLL6_CTRL_K_MASK) >> CCM_PLL6_CTRL_K_SHIFT) + 1; in clock_get_pll6()
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| A D | clock_sun6i.c | 305 uint32_t rval = readl(&ccm->pll3_cfg); in clock_get_pll3() local
306 int n = ((rval & CCM_PLL3_CTRL_N_MASK) >> CCM_PLL3_CTRL_N_SHIFT) + 1; in clock_get_pll3()
307 int m = ((rval & CCM_PLL3_CTRL_M_MASK) >> CCM_PLL3_CTRL_M_SHIFT) + 1; in clock_get_pll3()
317 uint32_t rval = readl(&ccm->pll6_cfg); in clock_get_pll6() local
318 int n = ((rval & CCM_PLL6_CTRL_N_MASK) >> CCM_PLL6_CTRL_N_SHIFT) + 1; in clock_get_pll6()
319 int k = ((rval & CCM_PLL6_CTRL_K_MASK) >> CCM_PLL6_CTRL_K_SHIFT) + 1; in clock_get_pll6()
327 uint32_t rval = readl(&ccm->mipi_pll_cfg); in clock_get_mipi_pll() local
328 unsigned int n = ((rval & CCM_MIPI_PLL_CTRL_N_MASK) >> CCM_MIPI_PLL_CTRL_N_SHIFT) + 1; in clock_get_mipi_pll()
329 unsigned int k = ((rval & CCM_MIPI_PLL_CTRL_K_MASK) >> CCM_MIPI_PLL_CTRL_K_SHIFT) + 1; in clock_get_mipi_pll()
330 unsigned int m = ((rval & CCM_MIPI_PLL_CTRL_M_MASK) >> CCM_MIPI_PLL_CTRL_M_SHIFT) + 1; in clock_get_mipi_pll()
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| A D | clock_sun50i_h6.c | 96 uint32_t rval = readl(&ccm->pll6_cfg); in clock_get_pll6() local
97 int n = ((rval & CCM_PLL6_CTRL_N_MASK) >> CCM_PLL6_CTRL_N_SHIFT); in clock_get_pll6()
98 int div1 = ((rval & CCM_PLL6_CTRL_DIV1_MASK) >> in clock_get_pll6()
100 int div2 = ((rval & CCM_PLL6_CTRL_DIV2_MASK) >> in clock_get_pll6()
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| A D | clock_sun8i_a83t.c | 129 uint32_t rval = readl(&ccm->pll6_cfg); in clock_get_pll6() local
130 int n = ((rval & CCM_PLL6_CTRL_N_MASK) >> CCM_PLL6_CTRL_N_SHIFT); in clock_get_pll6()
131 int div1 = ((rval & CCM_PLL6_CTRL_DIV1_MASK) >> in clock_get_pll6()
133 int div2 = ((rval & CCM_PLL6_CTRL_DIV2_MASK) >> in clock_get_pll6()
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| A D | clock_sun9i.c | 202 uint32_t rval = readl(&ccm->pll4_periph0_cfg); in clock_get_pll4_periph0() local
203 int n = ((rval & CCM_PLL4_CTRL_N_MASK) >> CCM_PLL4_CTRL_N_SHIFT); in clock_get_pll4_periph0()
204 int p = ((rval & CCM_PLL4_CTRL_P_MASK) >> CCM_PLL4_CTRL_P_SHIFT); in clock_get_pll4_periph0()
205 int m = ((rval & CCM_PLL4_CTRL_M_MASK) >> CCM_PLL4_CTRL_M_SHIFT) + 1; in clock_get_pll4_periph0()
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| A D | dram_sun8i_a83t.c | 267 u32 i, rval; in mctl_channel_init() local
291 rval = 0x0; in mctl_channel_init()
293 rval = 0x2; in mctl_channel_init()
297 rval << 24); in mctl_channel_init()
299 rval << 24); in mctl_channel_init()
301 rval << 24); in mctl_channel_init()
303 rval << 24); in mctl_channel_init()
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| /u-boot/drivers/timer/ |
| A D | mpc83xx_timer.c | 74 u32 rval; in mftbu() local
76 asm volatile("mftbu %0" : "=r" (rval)); in mftbu()
77 return rval; in mftbu()
87 u32 rval; in mftb() local
89 asm volatile("mftb %0" : "=r" (rval)); in mftb()
90 return rval; in mftb()
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| /u-boot/arch/powerpc/include/asm/ |
| A D | processor.h | 1140 #define mfdcr(rn) ({unsigned int rval; \
1142 : "=r" (rval)); rval;})
1145 #define mfmsr() ({unsigned int rval; \
1146 asm volatile("mfmsr %0" : "=r" (rval)); rval;})
1149 #define mfspr(rn) ({unsigned int rval; \
1151 : "=r" (rval)); rval;})
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| /u-boot/drivers/mmc/ |
| A D | sunxi_mmc.c | 227 unsigned rval = readl(&priv->reg->clkcr); in mmc_config_clock() local
230 rval &= ~SUNXI_MMC_CLK_ENABLE; in mmc_config_clock()
231 writel(rval, &priv->reg->clkcr); in mmc_config_clock()
240 rval &= ~SUNXI_MMC_CLK_DIVIDER_MASK; in mmc_config_clock()
241 writel(rval, &priv->reg->clkcr); in mmc_config_clock()
254 rval |= SUNXI_MMC_CLK_ENABLE; in mmc_config_clock()
255 writel(rval, &priv->reg->clkcr); in mmc_config_clock()
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| /u-boot/drivers/phy/marvell/ |
| A D | comphy_a3700.c | 145 u32 rval = 0xDEAD, timeout; in comphy_poll_reg() local
149 rval = readw(addr); /* 16 bit */ in comphy_poll_reg()
151 rval = readl(addr) ; /* 32 bit */ in comphy_poll_reg()
153 if ((rval & mask) == val) in comphy_poll_reg()
159 debug("Time out waiting (%p = %#010x)\n", addr, rval); in comphy_poll_reg()
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| /u-boot/arch/powerpc/cpu/mpc83xx/ |
| A D | spd_sdram.c | 857 u32 rval; in mftbu() local
859 asm volatile("mftbu %0" : "=r" (rval)); in mftbu()
860 return rval; in mftbu()
865 u32 rval; in mftb() local
867 asm volatile("mftb %0" : "=r" (rval)); in mftb()
868 return rval; in mftb()
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| /u-boot/drivers/ddr/altera/ |
| A D | sdram_gen5.c | 263 u32 rval; in sdram_write_verify() local
269 rval = readl(addr); in sdram_write_verify()
270 if (rval != val) { in sdram_write_verify()
272 addr, val, rval); in sdram_write_verify()
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| /u-boot/drivers/net/ |
| A D | fsl_mcdmafec.c | 236 int rval, i; in fec_init() local
265 rval = eth_env_get_enetaddr("ethaddr", enetaddr); in fec_init()
267 rval = eth_env_get_enetaddr("eth1addr", enetaddr); in fec_init()
269 if (!rval) { in fec_init()
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| A D | mcffec.c | 281 int rval, i; in mcffec_init() local
307 rval = eth_env_get_enetaddr("ethaddr", ea); in mcffec_init()
309 rval = eth_env_get_enetaddr("eth1addr", ea); in mcffec_init()
311 if (!rval) { in mcffec_init()
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| /u-boot/arch/arm/mach-socfpga/ |
| A D | clock_manager_arria10.c | 931 int rval; in cm_basic_init() local
937 rval = of_get_clk_cfg(blob, &main_cfg, &per_cfg); in cm_basic_init()
938 if (rval) in cm_basic_init()
939 return rval; in cm_basic_init()
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| /u-boot/scripts/kconfig/ |
| A D | expr.c | 1031 union string_value lval = {}, rval = {}; in expr_calc_value() local
1071 k2 = expr_parse_string(str2, e->right.sym->type, &rval); in expr_calc_value()
1083 res = (lval.u > rval.u) - (lval.u < rval.u); in expr_calc_value()
1085 res = (lval.s > rval.s) - (lval.s < rval.s); in expr_calc_value()
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| /u-boot/common/ |
| A D | dlmalloc.c | 74 BOOL rval; in gcleanup() local
78 rval = VirtualFree ((void*)gAddressBase, in gcleanup()
81 assert (rval); in gcleanup()
86 rval = VirtualFree (head->base, 0, MEM_RELEASE); in gcleanup()
87 assert (rval); in gcleanup()
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| A D | dlmalloc.src | 987 BOOL rval;
991 rval = VirtualFree ((void*)gAddressBase,
994 assert (rval);
999 rval = VirtualFree (head->base, 0, MEM_RELEASE);
1000 assert (rval);
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