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Searched refs:rwcfg (Results 1 – 2 of 2) sorted by relevance

/u-boot/drivers/ddr/altera/
A Dsequencer.c847 writel(seq->rwcfg->idle_loop1, in delay_for_n_mem_clocks()
859 writel(seq->rwcfg->idle_loop2, in delay_for_n_mem_clocks()
862 writel(seq->rwcfg->idle_loop2, in delay_for_n_mem_clocks()
866 writel(seq->rwcfg->idle_loop2, in delay_for_n_mem_clocks()
932 writel(seq->rwcfg->emr2, grpaddr); in rw_mgr_mem_load_user_ddr2()
934 writel(seq->rwcfg->emr, grpaddr); in rw_mgr_mem_load_user_ddr2()
952 writel(seq->rwcfg->emr, grpaddr); in rw_mgr_mem_load_user_ddr2()
1132 seq->rwcfg->mrs0_user, 1); in rw_mgr_mem_handoff()
1536 writel(seq->rwcfg->read_b2b, in rw_mgr_mem_calibrate_read_test()
1545 writel(seq->rwcfg->read_b2b, in rw_mgr_mem_calibrate_read_test()
[all …]
A Dsequencer.h9 #define RW_MGR_NUM_DM_PER_WRITE_GROUP (seq->rwcfg->mem_data_mask_width \
10 / seq->rwcfg->mem_if_write_dqs_width)
12 seq->rwcfg->true_mem_data_mask_width \
13 / seq->rwcfg->mem_if_write_dqs_width)
15 #define RW_MGR_NUM_DQS_PER_WRITE_GROUP (seq->rwcfg->mem_if_read_dqs_width \
16 / seq->rwcfg->mem_if_write_dqs_width)
17 #define NUM_RANKS_PER_SHADOW_REG (seq->rwcfg->mem_number_of_ranks \
262 const struct socfpga_sdram_rw_mgr_config *rwcfg; member

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