Searched refs:rx_ctl (Results 1 – 3 of 3) sorted by relevance
39 u32 rx_ctl; /* 0x3c */ member295 writel(EMAC_RX_SETUP, ®s->rx_ctl); in emac_setup()356 setbits_le32(®s->rx_ctl, 0x8); in _sunxi_emac_eth_init()440 setbits_le32(®s->rx_ctl, 0x1 << 3); in _sunxi_emac_eth_recv()441 while (readl(®s->rx_ctl) & (0x1 << 3)) in _sunxi_emac_eth_recv()
368 u16 rx_ctl; in asix_basic_reset() local396 rx_ctl = asix_read_rx_ctl(dev); in asix_basic_reset()397 debug("RX_CTL is 0x%04x after software reset\n", rx_ctl); in asix_basic_reset()401 rx_ctl = asix_read_rx_ctl(dev); in asix_basic_reset()402 debug("RX_CTL is 0x%04x setting to 0x0000\n", rx_ctl); in asix_basic_reset()
977 u64 rx_ctl; in bgx_poll_for_link() local982 rx_ctl = bgx_reg_read(lmac->bgx, lmac->lmacid, BGX_SMUX_RX_CTL); in bgx_poll_for_link()999 ((rx_ctl & SMU_RX_CTL_STATUS) == 0)) { in bgx_poll_for_link()
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