Searched refs:s3 (Results 1 – 23 of 23) sorted by relevance
| /u-boot/lib/lzo/ |
| A D | lzodefs.h | 43 #define DX3(p, s1, s2, s3) ((DX2((p)+1, s2, s3) << (s1)) ^ (p)[0]) argument
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| /u-boot/test/lib/ |
| A D | sscanf.c | 39 char s1[20], s2[10], s3[10], ch; in lib_sscanf() local
151 ut_asserteq(2, sscanf("WD40", "%2s%u", s3, &u1)); /* %s%u */ in lib_sscanf()
152 ut_asserteq_str(s3, "WD"); in lib_sscanf()
154 ut_asserteq(2, sscanf("WD40", "%3s%u", s3, &u1)); /* %s%u */ in lib_sscanf()
155 ut_asserteq_str(s3, "WD4"); in lib_sscanf()
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| /u-boot/arch/mips/include/asm/ |
| A D | regdef.h | 42 #define s3 $19 macro
85 #define s3 $19 macro
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| /u-boot/arch/riscv/lib/ |
| A D | setjmp.S | 23 STORE_IDX(s3, 3)
44 LOAD_IDX(s3, 3)
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| A D | interrupts.c | 42 regs->a7, regs->s2, regs->s3); in show_regs()
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| /u-boot/configs/ |
| A D | pinecube_defconfig | 9 CONFIG_DEFAULT_DEVICE_TREE="sun8i-s3-pinecube"
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| /u-boot/arch/arm/dts/ |
| A D | sun8i-s3-lichee-zero-plus.dts | 13 compatible = "sipeed,lichee-zero-plus", "sochip,s3",
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| A D | vexpress-v2p-ca9.dts | 233 volt-vd10-s3 {
276 amp-vd10-s3 {
290 power-vd10-s3 {
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| A D | sun8i-s3-pinecube.dts | 13 compatible = "pine64,pinecube", "allwinner,sun8i-s3";
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| A D | rk3399-nanopi4.dtsi | 51 vcc1v8_s3: vcc1v8-s3 {
78 vcca0v9_s3: vcca0v9-s3 {
87 vcca1v8_s3: vcca1v8-s3 {
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| A D | rk3399-pinebook-pro.dts | 257 vcca1v8_s3: vcc1v8-s3 {
352 vcca0v9_s3: vcca0v9-s3 {
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| A D | rk3399-khadas-edge.dtsi | 42 vcc1v8_s3: vcca1v8_s3: vcc1v8-s3 {
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| A D | rk3399-firefly.dts | 149 vcc1v8_s3: vcca1v8_s3: vcc1v8-s3 {
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| A D | rk3399-rockpro64.dtsi | 89 vcc1v8_s3: vcca1v8_s3: vcc1v8-s3 {
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| A D | rk3399-orangepi.dts | 95 vcc1v8_s3: vcca1v8_s3: vcc1v8-s3 {
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| A D | rk3399-roc-pc.dtsi | 114 vcc1v8_s3: vcca1v8_s3: vcc1v8-s3 {
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| A D | Makefile | 599 sun8i-s3-pinecube.dtb \
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| /u-boot/arch/riscv/include/asm/ |
| A D | ptrace.h | 32 unsigned long s3; member
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| /u-boot/arch/riscv/cpu/ |
| A D | start.S | 260 mv s3, a1 /* save addr of gd */
371 mv a2, s3
398 mv a0, s3 /* gd_t */
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| /u-boot/arch/mips/lib/ |
| A D | cache_init.S | 117 #define R_DC_SIZE s3
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| /u-boot/doc/device-tree-bindings/fsp/fsp2/apollolake/ |
| A D | fsp-m.txt | 241 - fspm,enable-s3-heci2: Enable HECI2 in S3 resume path
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| A D | fsp-s.txt | 457 - fsps,init-s3-cpu: Init CPU during S3 resume
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| /u-boot/arch/x86/dts/ |
| A D | chromebook_coral.dts | 765 fspm,enable-s3-heci2 = <0>;
907 slp-s3-assertion-width-usecs = <28000>;
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