| /u-boot/drivers/serial/ |
| A D | serial_cortina.c | 68 unsigned int uart_ctrl, baud, sample; in ca_serial_setbrg() local
77 sample = baud / 2; in ca_serial_setbrg()
78 sample = (sample < 7) ? 7 : sample; in ca_serial_setbrg()
79 writel(sample, priv->base + URX_SAMPLE); in ca_serial_setbrg()
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| /u-boot/board/bosch/shc/ |
| A D | Kconfig | 52 activate, if you want to build for the B sample version
58 activate, if you want to build for the B2 sample version
64 activate, if you want to build for the C sample version
70 activate, if you want to build for the C2 sample version
76 activate, if you want to build for the C3 sample version
|
| /u-boot/doc/device-tree-bindings/exynos/ |
| A D | sound.txt | 10 - samsung,i2s-bits-per-sample : sample width, defalut is 16 bit
22 samsung,i2s-bits-per-sample = <16>;
|
| A D | dwmmc.txt | 30 Drv/sample clock selection register of corresponding channel.
33 . SelClk_sample: Select sample clock among 8 shifted clocks.
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| /u-boot/arch/x86/cpu/quark/ |
| A D | mrc_util.c | 1095 uint8_t sample; /* sample counter */ in find_rising_edge() local
1110 for (sample = 0; sample < SAMPLE_CNT; sample++) { in find_rising_edge()
1116 delay[bl] + sample * SAMPLE_DLY); in find_rising_edge()
1119 delay[bl] + sample * SAMPLE_DLY); in find_rising_edge()
1124 sample_result[sample] = sample_dqs(mrc_params, in find_rising_edge()
1129 rcvn ? "RCVN" : "WDQS", channel, rank, sample, in find_rising_edge()
1130 sample * SAMPLE_DLY, sample_result[sample]); in find_rising_edge()
1140 for (sample = 0; sample < SAMPLE_CNT; sample++) { in find_rising_edge()
1142 ((sample_result[sample] & (1 << bl)) >> bl) << in find_rising_edge()
1143 (SAMPLE_CNT - 1 - sample); in find_rising_edge()
|
| /u-boot/drivers/adc/ |
| A D | Kconfig | 21 - 600 KSPS of sample rate
40 - Up to 1MSPS of sample rate
49 - Up to 1MSPS of sample rate
|
| /u-boot/arch/arm/dts/ |
| A D | exynos5250.dtsi | 89 samsung,i2s-bits-per-sample = <16>;
103 samsung,i2s-bits-per-sample = <16>;
|
| A D | stm32mp157c-odyssey.dts | 50 st,min-sample-time-nsecs = <5000>;
58 st,min-sample-time-nsecs = <5000>;
|
| A D | stm32f429-disco.dts | 89 st,sample-time = <4>;
93 /* 8 sample average control */
|
| A D | socfpga_cyclone5_mcvevk.dts | 62 ts,sample-time = <4>;
|
| A D | sun8i-s3-pinecube.dts | 76 pclk-sample = <1>; /* Rising */
127 pclk-sample = <1>; /* Rising */
|
| A D | sun8i-h3.dtsi | 251 "sample";
263 "sample";
275 "sample";
|
| A D | imx53-m53.dtsi | 60 st,sample-time = <4>;
|
| /u-boot/doc/device-tree-bindings/video/ |
| A D | display-timing.txt | 31 sample data on falling edge
33 sample data on rising edge
|
| /u-boot/doc/board/intel/ |
| A D | bayleybay.rst | 16 from the sample SPI image provided in the FSP (SPI.bin at the time of writing)::
|
| /u-boot/board/Marvell/dreamplug/ |
| A D | kwbimage.cfg | 38 # bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
110 # bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz
|
| /u-boot/board/Marvell/guruplug/ |
| A D | kwbimage.cfg | 37 # bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
109 # bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz
|
| /u-boot/board/Marvell/sheevaplug/ |
| A D | kwbimage.cfg | 37 # bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
109 # bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz
|
| /u-boot/board/Synology/ds109/ |
| A D | kwbimage.cfg | 41 # bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
113 # bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz
|
| /u-boot/board/Seagate/dockstar/ |
| A D | kwbimage.cfg | 40 # bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
112 # bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz
|
| /u-boot/board/Seagate/goflexhome/ |
| A D | kwbimage.cfg | 43 # bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
115 # bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz
|
| /u-boot/board/Marvell/openrd/ |
| A D | kwbimage.cfg | 37 # bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
109 # bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz
|
| /u-boot/board/cloudengines/pogo_e02/ |
| A D | kwbimage.cfg | 41 # bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
113 # bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz
|
| /u-boot/board/iomega/iconnect/ |
| A D | kwbimage.cfg | 37 # bit27-24: 0x7, CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
109 # bit8: 0x1, add writepath sample stage, must be 1 for DDR freq >= 300MHz
|
| /u-boot/board/keymile/km_arm/ |
| A D | kwbimage.cfg | 58 # bit27-24: 6= CL+3, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
121 # bit8 : 0 , no sample stage
|