Home
last modified time | relevance | path

Searched refs:sdhci_readl (Results 1 – 6 of 6) sorted by relevance

/u-boot/drivers/mmc/
A Dxenon_sdhci.c157 var = sdhci_readl(host, SDHCI_CLOCK_CONTROL); in xenon_mmc_phy_init()
245 ctrl = sdhci_readl(host, SDHC_SLOT_EMMC_CTRL); in xenon_mmc_start_signal_voltage_switch()
264 var = sdhci_readl(host, EMMC_PHY_PAD_CONTROL); in xenon_mmc_phy_set()
295 var = sdhci_readl(host, SDHCI_CLOCK_CONTROL); in xenon_mmc_phy_set()
309 var = sdhci_readl(host, SDHCI_CLOCK_CONTROL); in xenon_mmc_phy_set()
321 var = sdhci_readl(host, SDHC_SYS_OP_CTRL); in xenon_mmc_set_acg()
337 var = sdhci_readl(host, SDHC_SYS_OP_CTRL); in xenon_mmc_enable_slot()
347 var = sdhci_readl(host, SDHC_SYS_OP_CTRL); in xenon_mmc_disable_slot()
357 var = sdhci_readl(host, SDHC_SYS_EXT_OP_CTRL); in xenon_mmc_enable_parallel_tran()
372 var = sdhci_readl(host, SDHCI_SIGNAL_ENABLE); in xenon_mmc_disable_tuning()
[all …]
A Dkona_sdhci.c34 mask = sdhci_readl(host, SDHCI_CORECTRL_OFFSET) | SDHCI_CORECTRL_RESET; in init_kona_mmc_core()
47 (sdhci_readl(host, SDHCI_CORECTRL_OFFSET) & in init_kona_mmc_core()
55 mask = sdhci_readl(host, SDHCI_CORECTRL_OFFSET); in init_kona_mmc_core()
62 mask = sdhci_readl(host, SDHCI_CORESTAT_OFFSET); in init_kona_mmc_core()
67 while (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) { in init_kona_mmc_core()
A Dsdhci.c49 cmd->response[i] = sdhci_readl(host, in sdhci_cmd_done()
56 cmd->response[0] = sdhci_readl(host, SDHCI_RESPONSE); in sdhci_cmd_done()
67 *(u32 *)offs = sdhci_readl(host, SDHCI_BUFFER); in sdhci_transfer_pio()
139 stat = sdhci_readl(host, SDHCI_INT_STATUS); in sdhci_transfer_data()
303 stat = sdhci_readl(host, SDHCI_INT_STATUS);
330 stat = sdhci_readl(host, SDHCI_INT_STATUS);
372 while (sdhci_readl(host, SDHCI_PRESENT_STATE) &
804 sdhci_readl(host, SDHCI_CAPABILITIES);
807 caps = sdhci_readl(host, SDHCI_CAPABILITIES);
836 sdhci_readl(host, SDHCI_HOST_VERSION - 2) >> 16;
[all …]
A Ds5p_sdhci.c43 val = sdhci_readl(host, SDHCI_CONTROL2); in s5p_sdhci_set_control_reg()
71 ctrl = sdhci_readl(host, SDHCI_CONTROL2); in s5p_sdhci_set_control_reg()
A Dzynq_sdhci.c345 regval = sdhci_readl(host, SDHCI_ARASAN_OTAPDLY_REGISTER); in sdhci_versal_sdcardclk_set_phase()
409 regval = sdhci_readl(host, SDHCI_ARASAN_ITAPDLY_REGISTER); in sdhci_versal_sampleclk_set_phase()
/u-boot/include/
A Dsdhci.h366 static inline u32 sdhci_readl(struct sdhci_host *host, int reg) in sdhci_readl() function
406 static inline u32 sdhci_readl(struct sdhci_host *host, int reg) in sdhci_readl() function

Completed in 11 milliseconds