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Searched refs:sdhci_writel (Results 1 – 7 of 7) sorted by relevance

/u-boot/drivers/mmc/
A Dkona_sdhci.c35 sdhci_writel(host, mask, SDHCI_CORECTRL_OFFSET); in init_kona_mmc_core()
52 sdhci_writel(host, mask, SDHCI_CORECTRL_OFFSET); in init_kona_mmc_core()
56 sdhci_writel(host, mask | SDHCI_CORECTRL_EN, SDHCI_CORECTRL_OFFSET); in init_kona_mmc_core()
59 sdhci_writel(host, SDHCI_COREIMR_IP, SDHCI_COREIMR_OFFSET); in init_kona_mmc_core()
63 sdhci_writel(host, mask | SDHCI_CORESTAT_CD_SW, SDHCI_CORESTAT_OFFSET); in init_kona_mmc_core()
A Dxenon_sdhci.c151 sdhci_writel(host, var, EMMC_PHY_TIMING_ADJUST); in xenon_mmc_phy_init()
172 sdhci_writel(host, var, EMMC_PHY_TIMING_ADJUST); in xenon_mmc_phy_init()
250 sdhci_writel(host, ctrl, SDHC_SLOT_EMMC_CTRL); in xenon_mmc_start_signal_voltage_switch()
267 sdhci_writel(host, var, EMMC_PHY_PAD_CONTROL); in xenon_mmc_phy_set()
273 sdhci_writel(host, var, EMMC_PHY_PAD_CONTROL1); in xenon_mmc_phy_set()
327 sdhci_writel(host, var, SDHC_SYS_OP_CTRL); in xenon_mmc_set_acg()
339 sdhci_writel(host, var, SDHC_SYS_OP_CTRL); in xenon_mmc_enable_slot()
349 sdhci_writel(host, var, SDHC_SYS_OP_CTRL); in xenon_mmc_disable_slot()
359 sdhci_writel(host, var, SDHC_SYS_EXT_OP_CTRL); in xenon_mmc_enable_parallel_tran()
374 sdhci_writel(host, var, SDHCI_SIGNAL_ENABLE); in xenon_mmc_disable_tuning()
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A Dzynq_sdhci.c124 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE); in arasan_sdhci_execute_tuning()
125 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE); in arasan_sdhci_execute_tuning()
159 sdhci_writel(host, ctrl, SDHCI_HOST_CONTROL2); in arasan_sdhci_execute_tuning()
171 sdhci_writel(host, SDHCI_INT_DATA_MASK | SDHCI_INT_CMD_MASK, in arasan_sdhci_execute_tuning()
174 sdhci_writel(host, 0x0, SDHCI_SIGNAL_ENABLE); in arasan_sdhci_execute_tuning()
347 sdhci_writel(host, regval, SDHCI_ARASAN_OTAPDLY_REGISTER); in sdhci_versal_sdcardclk_set_phase()
349 sdhci_writel(host, regval, SDHCI_ARASAN_OTAPDLY_REGISTER); in sdhci_versal_sdcardclk_set_phase()
411 sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER); in sdhci_versal_sampleclk_set_phase()
413 sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER); in sdhci_versal_sampleclk_set_phase()
415 sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER); in sdhci_versal_sampleclk_set_phase()
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A Ds5p_sdhci.c41 sdhci_writel(host, SDHCI_CTRL4_DRIVE_MASK(0x3), SDHCI_CONTROL4); in s5p_sdhci_set_control_reg()
51 sdhci_writel(host, val, SDHCI_CONTROL2); in s5p_sdhci_set_control_reg()
63 sdhci_writel(host, val, SDHCI_CONTROL3); in s5p_sdhci_set_control_reg()
74 sdhci_writel(host, ctrl, SDHCI_CONTROL2); in s5p_sdhci_set_control_reg()
A Dsdhci.c69 sdhci_writel(host, *(u32 *)offs, SDHCI_BUFFER); in sdhci_transfer_pio()
109 sdhci_writel(host, dma_addr, SDHCI_DMA_ADDRESS); in sdhci_prepare_dma()
116 sdhci_writel(host, lower_32_bits(host->adma_addr), in sdhci_prepare_dma()
119 sdhci_writel(host, upper_32_bits(host->adma_addr), in sdhci_prepare_dma()
148 sdhci_writel(host, rdy, SDHCI_INT_STATUS); in sdhci_transfer_data()
162 sdhci_writel(host, SDHCI_INT_DMA_END, SDHCI_INT_STATUS); in sdhci_transfer_data()
169 sdhci_writel(host, start_addr, SDHCI_DMA_ADDRESS); in sdhci_transfer_data()
248 sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
299 sdhci_writel(host, cmd->cmdarg, SDHCI_ARGUMENT);
320 sdhci_writel(host, mask, SDHCI_INT_STATUS);
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A Diproc_sdhci.c167 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE); in sdhci_start_tuning()
168 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE); in sdhci_start_tuning()
174 sdhci_writel(host, SDHCI_INT_DATA_MASK | SDHCI_INT_CMD_MASK, in sdhci_end_tuning()
177 sdhci_writel(host, 0x0, SDHCI_SIGNAL_ENABLE); in sdhci_end_tuning()
221 sdhci_writel(host, ctrl, SDHCI_HOST_CONTROL2); in sdhci_iproc_execute_tuning()
/u-boot/include/
A Dsdhci.h342 static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg) in sdhci_writel() function
392 static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg) in sdhci_writel() function

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