Home
last modified time | relevance | path

Searched refs:sdram (Results 1 – 25 of 119) sorted by relevance

12345

/u-boot/board/freescale/m54418twr/
A Dm54418twr.c63 out_be32(&sdram->cr00, 0x01010101); in dram_init()
64 out_be32(&sdram->cr01, 0x00000101); in dram_init()
65 out_be32(&sdram->cr02, 0x01010100); in dram_init()
66 out_be32(&sdram->cr03, 0x01010000); in dram_init()
67 out_be32(&sdram->cr04, 0x00010101); in dram_init()
68 out_be32(&sdram->cr06, 0x00010100); in dram_init()
69 out_be32(&sdram->cr07, 0x00000001); in dram_init()
70 out_be32(&sdram->cr08, 0x01000001); in dram_init()
71 out_be32(&sdram->cr09, 0x00000100); in dram_init()
72 out_be32(&sdram->cr10, 0x00010001); in dram_init()
[all …]
/u-boot/board/freescale/m53017evb/
A Dm53017evb.c29 sdram_t *sdram = (sdram_t *)(MMAP_SDRAM); in dram_init() local
40 out_be32(&sdram->cs0, CONFIG_SYS_SDRAM_BASE | i); in dram_init()
42 out_be32(&sdram->cs1, CONFIG_SYS_SDRAM_BASE | i); in dram_init()
44 out_be32(&sdram->cfg1, CONFIG_SYS_SDRAM_CFG1); in dram_init()
45 out_be32(&sdram->cfg2, CONFIG_SYS_SDRAM_CFG2); in dram_init()
50 out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2); in dram_init()
54 out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4); in dram_init()
55 out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4); in dram_init()
59 out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE); in dram_init()
61 out_be32(&sdram->mode, CONFIG_SYS_SDRAM_EMOD); in dram_init()
[all …]
/u-boot/board/freescale/m5329evb/
A Dm5329evb.c29 sdram_t *sdram = (sdram_t *)(MMAP_SDRAM); in dram_init() local
40 out_be32(&sdram->cs0, CONFIG_SYS_SDRAM_BASE | i); in dram_init()
41 out_be32(&sdram->cfg1, CONFIG_SYS_SDRAM_CFG1); in dram_init()
42 out_be32(&sdram->cfg2, CONFIG_SYS_SDRAM_CFG2); in dram_init()
45 out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2); in dram_init()
48 out_be32(&sdram->mode, CONFIG_SYS_SDRAM_EMOD); in dram_init()
54 out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2); in dram_init()
57 out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4); in dram_init()
58 out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4); in dram_init()
60 out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE); in dram_init()
[all …]
/u-boot/board/freescale/m5373evb/
A Dm5373evb.c29 sdram_t *sdram = (sdram_t *)(MMAP_SDRAM); in dram_init() local
40 out_be32(&sdram->cs0, CONFIG_SYS_SDRAM_BASE | i); in dram_init()
41 out_be32(&sdram->cfg1, CONFIG_SYS_SDRAM_CFG1); in dram_init()
42 out_be32(&sdram->cfg2, CONFIG_SYS_SDRAM_CFG2); in dram_init()
45 out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2); in dram_init()
48 out_be32(&sdram->mode, CONFIG_SYS_SDRAM_EMOD); in dram_init()
54 out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2); in dram_init()
57 out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4); in dram_init()
58 out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4); in dram_init()
60 out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE); in dram_init()
[all …]
/u-boot/board/freescale/m5208evbe/
A Dm5208evbe.c29 sdram_t *sdram = (sdram_t *)(MMAP_SDRAM); in dram_init() local
40 out_be32(&sdram->cs0, CONFIG_SYS_SDRAM_BASE | i); in dram_init()
42 out_be32(&sdram->cs1, CONFIG_SYS_SDRAM_BASE | i); in dram_init()
44 out_be32(&sdram->cfg1, CONFIG_SYS_SDRAM_CFG1); in dram_init()
45 out_be32(&sdram->cfg2, CONFIG_SYS_SDRAM_CFG2); in dram_init()
50 out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2); in dram_init()
54 out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4); in dram_init()
55 out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4); in dram_init()
59 out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE); in dram_init()
61 out_be32(&sdram->mode, CONFIG_SYS_SDRAM_EMOD); in dram_init()
[all …]
/u-boot/board/freescale/m54451evb/
A Dm54451evb.c41 sdramc_t *sdram = (sdramc_t *)(MMAP_SDRAM); in dram_init() local
48 (in_be32(&sdram->sdcfg2) == CONFIG_SYS_SDRAM_CFG2)) in dram_init()
59 out_be32(&sdram->sdcs0, CONFIG_SYS_SDRAM_BASE | i); in dram_init()
61 out_be32(&sdram->sdcfg1, CONFIG_SYS_SDRAM_CFG1); in dram_init()
62 out_be32(&sdram->sdcfg2, CONFIG_SYS_SDRAM_CFG2); in dram_init()
67 out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 2); in dram_init()
71 out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 4); in dram_init()
73 out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 4); in dram_init()
77 out_be32(&sdram->sdmr, CONFIG_SYS_SDRAM_MODE); in dram_init()
79 out_be32(&sdram->sdmr, CONFIG_SYS_SDRAM_MODE); in dram_init()
[all …]
/u-boot/board/freescale/m52277evb/
A Dm52277evb.c37 sdramc_t *sdram = (sdramc_t *)(MMAP_SDRAM); in dram_init() local
51 out_be32(&sdram->sdcs0, CONFIG_SYS_SDRAM_BASE | i); in dram_init()
53 out_be32(&sdram->sdcfg1, CONFIG_SYS_SDRAM_CFG1); in dram_init()
54 out_be32(&sdram->sdcfg2, CONFIG_SYS_SDRAM_CFG2); in dram_init()
57 out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 2); in dram_init()
61 out_be32(&sdram->sdmr, CONFIG_SYS_SDRAM_MODE); in dram_init()
63 out_be32(&sdram->sdmr, CONFIG_SYS_SDRAM_EMOD); in dram_init()
69 out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 2); in dram_init()
73 out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 4); in dram_init()
75 out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 4); in dram_init()
[all …]
/u-boot/board/freescale/m547xevb/
A Dm547xevb.c31 sdram_t *sdram = (sdram_t *)(MMAP_SDRAM); in dram_init() local
58 out_be32(&sdram->cfg1, CONFIG_SYS_SDRAM_CFG1); in dram_init()
59 out_be32(&sdram->cfg2, CONFIG_SYS_SDRAM_CFG2); in dram_init()
62 out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2); in dram_init()
65 out_be32(&sdram->mode, CONFIG_SYS_SDRAM_EMOD); in dram_init()
66 out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE | 0x04000000); in dram_init()
71 out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2); in dram_init()
74 out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4); in dram_init()
75 out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4); in dram_init()
77 out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE); in dram_init()
[all …]
/u-boot/board/freescale/m548xevb/
A Dm548xevb.c31 sdram_t *sdram = (sdram_t *)(MMAP_SDRAM); in dram_init() local
58 out_be32(&sdram->cfg1, CONFIG_SYS_SDRAM_CFG1); in dram_init()
59 out_be32(&sdram->cfg2, CONFIG_SYS_SDRAM_CFG2); in dram_init()
62 out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2); in dram_init()
65 out_be32(&sdram->mode, CONFIG_SYS_SDRAM_EMOD); in dram_init()
66 out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE | 0x04000000); in dram_init()
71 out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2); in dram_init()
74 out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4); in dram_init()
75 out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4); in dram_init()
77 out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE); in dram_init()
[all …]
/u-boot/doc/device-tree-bindings/memory-controllers/
A Dst,stm32-fmc.txt8 on-board sdram memory attributes:
9 - st,sdram-control : parameters for sdram configuration, in this order:
18 - st,sdram-timing: timings for sdram, in this order:
27 include/dt-bindings/memory/stm32-sdram.h to define sdram control and timing
43 /* sdram memory configuration from sdram datasheet */
45 st,sdram-control = /bits/ 8 <NO_COL_8 NO_ROW_12 MWIDTH_16 BANKS_2
47 st,sdram-timing = /bits/ 8 <TMRD_1 TXSR_60 TRAS_42 TRC_60 TRP_18
51 /* sdram memory configuration from sdram datasheet */
53 st,sdram-control = /bits/ 8 <NO_COL_8 NO_ROW_12 MWIDTH_16 BANKS_2
55 st,sdram-timing = /bits/ 8 <TMRD_1 TXSR_60 TRAS_42 TRC_60 TRP_18
/u-boot/board/freescale/m5235evb/
A Dm5235evb.c28 sdram_t *sdram = (sdram_t *)(MMAP_SDRAM); in dram_init() local
54 if (!(in_be32(&sdram->dacr0) & SDRAMC_DARCn_RE)) { in dram_init()
58 out_be16(&sdram->dcr, SDRAMC_DCR_RTIM_9CLKS | in dram_init()
63 out_be32(&sdram->dacr0, in dram_init()
70 out_be32(&sdram->dmr0, in dram_init()
75 setbits_be32(&sdram->dacr0, SDRAMC_DARCn_IP); in dram_init()
86 setbits_be32(&sdram->dacr0, SDRAMC_DARCn_RE); in dram_init()
94 setbits_be32(&sdram->dacr0, SDRAMC_DARCn_IMRS); in dram_init()
/u-boot/board/freescale/m54455evb/
A Dm54455evb.c37 sdramc_t *sdram = (sdramc_t *)(MMAP_SDRAM); in dram_init() local
51 out_be32(&sdram->sdcs0, CONFIG_SYS_SDRAM_BASE | i); in dram_init()
52 out_be32(&sdram->sdcs1, CONFIG_SYS_SDRAM_BASE1 | i); in dram_init()
54 out_be32(&sdram->sdcfg1, CONFIG_SYS_SDRAM_CFG1); in dram_init()
55 out_be32(&sdram->sdcfg2, CONFIG_SYS_SDRAM_CFG2); in dram_init()
58 out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 2); in dram_init()
61 out_be32(&sdram->sdmr, CONFIG_SYS_SDRAM_EMOD | 0x408); in dram_init()
67 out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 2); in dram_init()
70 out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 4); in dram_init()
71 out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 4); in dram_init()
[all …]
/u-boot/drivers/ram/rockchip/
A DKconfig9 bool "Enable rockchip sdram common driver"
12 This enable sdram common driver
29 This enables DDR4 sdram support instead of the default DDR3 support
36 This enables LPDDR2 sdram support instead of the default DDR3 support
43 This enables LPDDR3 sdram support instead of the default DDR3 support
50 This enables LPDDR4 sdram code support for the platforms based
/u-boot/arch/arm/cpu/armv8/
A Du-boot-spl.lds16 MEMORY { .sdram : ORIGIN = CONFIG_SPL_BSS_START_ADDR,
69 } >.sdram
74 } >.sdram
78 } >.sdram
/u-boot/arch/arm/mach-tegra/tegra20/
A Dwarmboot.c125 struct sdram_params sdram; in warmboot_save_sdram_params() local
142 memcpy(&sdram, in warmboot_save_sdram_params()
144 sizeof(sdram)); in warmboot_save_sdram_params()
168 scratch2.memory_type = sdram.memory_type; in warmboot_save_sdram_params()
175 scratch4.emc_clock_divider = sdram.emc_clock_divider; in warmboot_save_sdram_params()
182 scratch24.emc_pin_program_wait = sdram.emc_pin_program_wait; in warmboot_save_sdram_params()
183 scratch24.emc_auto_cal_wait = sdram.emc_auto_cal_wait; in warmboot_save_sdram_params()
184 scratch24.warmboot_wait = sdram.warm_boot_wait; in warmboot_save_sdram_params()
/u-boot/arch/m68k/cpu/mcf532x/
A Dspeed.c145 sdram_t *sdram = (sdram_t *)(MMAP_SDRAM); in clock_pll() local
201 if (in_be32(&sdram->ctrl) & SDRAMC_SDCR_REF) in clock_pll()
202 clrbits_be32(&sdram->ctrl, SDRAMC_SDCR_CKE); in clock_pll()
234 if (in_be32(&sdram->ctrl) & SDRAMC_SDCR_REF) in clock_pll()
235 setbits_be32(&sdram->ctrl, SDRAMC_SDCR_CKE); in clock_pll()
/u-boot/arch/arm/dts/
A Drk3399-puma-haikou-u-boot.dtsi6 #include "rk3399-sdram-ddr3-1333.dtsi"
9 #include "rk3399-sdram-ddr3-1600.dtsi"
12 #include "rk3399-sdram-ddr3-1866.dtsi"
A Dimxrt1020-evk.dts34 * Memory configuration from sdram datasheet IS42S16160J-6TLI
36 fsl,sdram-mux = /bits/ 8 <MUX_A8_SDRAM_A8
42 fsl,sdram-control = /bits/ 8 <MEM_WIDTH_16BITS
46 fsl,sdram-timing = /bits/ 8 <0x2
A Dstm32f429-disco-u-boot.dtsi7 #include <dt-bindings/memory/stm32-sdram.h>
45 * Memory configuration from sdram datasheet
49 st,sdram-control = /bits/ 8 <NO_COL_8
57 st,sdram-timing = /bits/ 8 <TMRD_3
63 st,sdram-refcount = < 1386 >;
/u-boot/arch/arm/cpu/arm1136/
A Du-boot-spl.lds13 MEMORY { .sdram : ORIGIN = CONFIG_SPL_BSS_START_ADDR, \
49 } >.sdram
/u-boot/arch/arm/mach-at91/
A DMakefile5 obj-$(CONFIG_AT91SAM9260) += sdram.o spl_at91.o
6 obj-$(CONFIG_AT91SAM9G20) += sdram.o spl_at91.o
/u-boot/arch/arm/mach-omap2/
A Du-boot-spl.lds13 MEMORY { .sdram : ORIGIN = CONFIG_SPL_BSS_START_ADDR, \
57 } >.sdram
/u-boot/board/davinci/da8xxevm/
A Du-boot-spl-da850evm.lds13 MEMORY { .sdram : ORIGIN = CONFIG_SPL_BSS_START_ADDR, \
64 } >.sdram
/u-boot/arch/arm/mach-at91/armv7/
A Du-boot-spl.lds16 MEMORY { .sdram : ORIGIN = CONFIG_SPL_BSS_START_ADDR, \
58 } >.sdram
/u-boot/arch/arm/mach-at91/arm926ejs/
A Du-boot-spl.lds9 MEMORY { .sdram : ORIGIN = CONFIG_SPL_BSS_START_ADDR, \
51 } >.sdram

Completed in 21 milliseconds

12345