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Searched refs:sdram_params (Results 1 – 8 of 8) sorted by relevance

/u-boot/drivers/ram/rockchip/
A Dsdram_px30.c255 if (sdram_params->base.dramtype == DDR4) in set_ctl_address_map()
430 &sdram_params->base); in dram_all_config()
452 if (sdram_params->base.dramtype == DDR4) in enable_low_power()
510 phy_cfg(dram->phy, &sdram_params->phy_regs, sdram_params->skew, in sdram_init_()
511 &sdram_params->base, cap_info->bw); in sdram_init_()
558 sdram_params->base.dramtype); in sdram_init_()
560 dram_all_config(dram, sdram_params); in sdram_init_()
561 enable_low_power(dram, sdram_params); in sdram_init_()
663 sdram_params->base.dramtype); in sdram_init_detect()
697 struct px30_sdram_params *sdram_params; in sdram_init() local
[all …]
A Dsdram_rk3288.c268 sdram_params->base.odt); in pctl_cfg()
350 if (sdram_params->base.odt) { in phy_cfg()
604 &sdram_params->ch[chan]; in dram_all_config()
638 sdram_params->num_channels = 1; in sdram_rank_bw_detect()
658 sdram_params->ch[channel].dbw = sdram_params->ch[channel].bw; in sdram_rank_bw_detect()
733 tmp = sdram_params->ch[0].col - 9; in sdram_get_niu_config()
744 sdram_params->base.ddrconfig = i; in sdram_get_niu_config()
755 (sdram_params->ch[0].cs0_row + in sdram_get_stride()
756 sdram_params->ch[0].col + in sdram_get_stride()
758 sdram_params->ch[0].bw + in sdram_get_stride()
[all …]
A Dsdram_rk3328.c45 struct rk3328_sdram_params sdram_params;
367 phy_cfg(dram->phy, &sdram_params->phy_regs, &sdram_params->skew, in sdram_init()
368 &sdram_params->base, cap_info->bw); in sdram_init()
385 sdram_params->base.dramtype); in sdram_init()
392 dram_all_config(dram, sdram_params); in sdram_init()
480 memcpy(&sdram_ch, &sdram_params->ch, in sdram_init_detect()
483 sdram_init(dram, sdram_params, 0); in sdram_init_detect()
488 sdram_params->base.dramtype); in sdram_init_detect()
496 sdram_init(dram, sdram_params, 1); in sdram_init_detect()
509 sdram_print_ddr_info(&sdram_params->ch.cap_info, &sdram_params->base); in sdram_init_detect()
[all …]
A Dsdram_rk3188.c291 if (sdram_params->base.odt) { in phy_cfg()
527 if (sdram_params->ch[chnum].bk == 3) in dram_cfg_rbc()
546 &sdram_params->ch[chan]; in dram_all_config()
560 if (sdram_params->ch[0].rank == 2) in dram_all_config()
596 sdram_params->ch[channel].bw = 1; in sdram_rank_bw_detect()
604 sdram_params->ch[channel].dbw = sdram_params->ch[channel].bw; in sdram_rank_bw_detect()
688 row = sdram_params->ch[0].cs0_row; in sdram_get_niu_config()
695 tmp = sdram_params->ch[0].col - 9; in sdram_get_niu_config()
707 sdram_params->base.ddrconfig = i; in sdram_get_niu_config()
756 sdram_params->ch[channel].bw = 2; in sdram_init()
[all …]
A Dsdram_rk322x.c410 if (sdram_params->ch[0].bw == 2) in pctl_cfg()
610 sdram_params->ch[0].dbw = 1; in dram_cap_detect()
612 sdram_params->ch[0].dbw = 2; in dram_cap_detect()
630 sdram_params->ch[0].bw = bw; in dram_cap_detect()
631 sdram_params->ch[0].bk = 3; in dram_cap_detect()
652 sdram_params->ch[0].col = col; in dram_cap_detect()
670 sdram_params->ch[0].cs1_row = row; in dram_cap_detect()
671 sdram_params->ch[0].row_3_4 = 0; in dram_cap_detect()
672 sdram_params->ch[0].cs0_row = row; in dram_cap_detect()
680 sdram_params->ch[0].rank = 2; in dram_cap_detect()
[all …]
A Dsdram_rk3399.c103 struct rk3399_sdram_params sdram_params;
3021 (u32 *)&plat->sdram_params, in rk3399_dmc_of_to_plat()
3022 sizeof(plat->sdram_params) / sizeof(u32)); in rk3399_dmc_of_to_plat()
3072 struct rk3399_sdram_params *params = &plat->sdram_params; in rk3399_dmc_init()
/u-boot/arch/arm/mach-tegra/tegra20/
A Dwarmboot.c125 struct sdram_params sdram; in warmboot_save_sdram_params()
143 (char *)((struct sdram_params *)SDRAM_PARAMS_BASE + ram_code), in warmboot_save_sdram_params()
/u-boot/arch/arm/include/asm/arch-tegra20/
A Dsdram_param.h27 struct sdram_params { struct

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