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Searched refs:sdram_tim1 (Results 1 – 25 of 27) sorted by relevance

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/u-boot/board/phytec/phycore_am335x_r2/
A Dboard.c80 .sdram_tim1 = 0x0AAAD4DB,
98 .sdram_tim1 = 0x0AAAD4DB,
116 .sdram_tim1 = 0x0AAAD4DB,
/u-boot/arch/arm/mach-omap2/omap4/
A Dsdram_elpida.c39 .sdram_tim1 = 0x08648311,
53 .sdram_tim1 = 0x10cb0622,
67 .sdram_tim1 = 0x10eb0662,
81 .sdram_tim1 = 0x10eb0662,
/u-boot/arch/arm/mach-omap2/omap5/
A Dsdram.c39 .sdram_tim1 = 0x772F6873,
58 .sdram_tim1 = 0x772F6873,
77 .sdram_tim1 = 0x2A86B419,
97 .sdram_tim1 = 0xCCCF36B3,
121 .sdram_tim1 = 0xCCCF36B3,
/u-boot/board/ti/am43xx/
A Dboard.c161 .sdram_tim1 = 0xEA86B411,
197 .sdram_tim1 = 0xEAAAD4DB,
223 .sdram_tim1 = 0xEAAAD4DB,
246 .sdram_tim1 = 0xEAAAD4DB,
269 .sdram_tim1 = 0xeaaad4db,
295 .sdram_tim1 = 0xeaaad4db,
/u-boot/board/siemens/draco/
A Dboard.h39 unsigned int sdram_tim1; /* 0x0888A39B */ member
A Dboard.c101 PRINTARGS(sdram_tim1); in print_ddr3_timings()
222 draco_ddr3_emif_reg_data.sdram_tim1 = settings.ddr3.sdram_tim1; in board_init_ddr()
/u-boot/board/ti/dra7xx/
A Devm.c76 .sdram_tim1 = 0xCCCF36B3,
101 .sdram_tim1 = 0xCCCF36B3,
126 .sdram_tim1 = 0xD113781C,
151 .sdram_tim1 = 0xD1137824,
176 .sdram_tim1 = 0xCCCF36B3,
201 .sdram_tim1 = 0xCCCF36B3,
226 .sdram_tim1 = 0xD113783C,
251 .sdram_tim1 = 0xD113781C,
/u-boot/board/isee/igep003x/
A Dboard.c112 .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
122 .sdram_tim1 = K4B2G1646EBIH9_EMIF_TIM1,
/u-boot/board/ti/am335x/
A Dboard.c117 .sdram_tim1 = MT47H128M16RT25E_EMIF_TIM1,
126 .sdram_tim1 = MT47H128M16RT25E_EMIF_TIM1,
208 .sdram_tim1 = MT41J128MJT125_EMIF_TIM1,
219 .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
230 .sdram_tim1 = MT41J512M8RH125_EMIF_TIM1,
242 .sdram_tim1 = MT41J128MJT125_EMIF_TIM1_400MHz,
/u-boot/board/compulab/cm_t43/
A Dspl.c38 .sdram_tim1 = 0xEAAAD4DB,
/u-boot/board/compulab/cm_t335/
A Dspl.c54 .sdram_tim1 = MT41J128MJT125_EMIF_TIM1,
/u-boot/board/BuR/brsmarc1/
A Dboard.c58 .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
/u-boot/board/ti/ti816x/
A Devm.c96 .sdram_tim1 = EMIF_TIM1,
/u-boot/board/BuR/brppt1/
A Dboard.c64 .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
/u-boot/board/BuR/brxre1/
A Dboard.c65 .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
/u-boot/board/bosch/guardian/
A Dboard.c67 .sdram_tim1 = MT41K128M16JT125K_EMIF_TIM1,
/u-boot/board/eets/pdu001/
A Dboard.c181 .sdram_tim1 = MT47H128M16RT25E_EMIF_TIM1,
/u-boot/arch/arm/mach-omap2/am33xx/
A Dchilisom.c88 .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
A Dddr.c222 writel(regs->sdram_tim1, &emif_reg[nr]->emif_sdram_tim_1); in set_sdram_timings()
223 writel(regs->sdram_tim1, &emif_reg[nr]->emif_sdram_tim_1_shdw); in set_sdram_timings()
/u-boot/board/ti/am57xx/
A Dboard.c140 .sdram_tim1 = 0xcccf36ab,
204 .sdram_tim1 = 0xcccf36b3,
267 .sdram_tim1 = 0xd333887c,
292 .sdram_tim1 = 0xd333887c,
/u-boot/arch/arm/mach-omap2/
A Demif-common.c178 writel(regs->sdram_tim1, &emif->emif_sdram_tim_1_shdw); in emif_update_timings()
429 writel(regs->sdram_tim1, &emif->emif_sdram_tim_1); in dra7_ddr3_init()
492 writel(regs->sdram_tim1, &emif->emif_sdram_tim_1); in omap5_ddr3_init()
987 regs->sdram_tim1 = get_sdram_tim_1_reg(timings, min_tck, addressing); in emif_calculate_regs()
1012 print_timing_reg(regs->sdram_tim1); in emif_calculate_regs()
/u-boot/board/tcl/sl50/
A Dboard.c66 .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
/u-boot/board/bosch/shc/
A Dboard.c423 .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
/u-boot/board/siemens/pxm2/
A Dboard.c50 .sdram_tim1 = 0x666b3c9, in board_init_ddr()
/u-boot/board/siemens/rut/
A Dboard.c55 .sdram_tim1 = 0x0888A39B, in board_init_ddr()

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