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Searched refs:sel (Results 1 – 25 of 75) sorted by relevance

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/u-boot/drivers/net/
A Dmdio_mux_sandbox.c17 int sel; member
20 static int mdio_mux_sandbox_mark_selection(struct udevice *dev, int sel) in mdio_mux_sandbox_mark_selection() argument
35 SANDBOX_PHY_REG_CNT - 1, (u16)sel); in mdio_mux_sandbox_mark_selection()
45 if (cur != priv->sel) in mdio_mux_sandbox_select()
48 priv->sel = sel; in mdio_mux_sandbox_select()
49 mdio_mux_sandbox_mark_selection(dev, priv->sel); in mdio_mux_sandbox_select()
54 static int mdio_mux_sandbox_deselect(struct udevice *dev, int sel) in mdio_mux_sandbox_deselect() argument
61 if (sel != priv->sel) in mdio_mux_sandbox_deselect()
64 priv->sel = -1; in mdio_mux_sandbox_deselect()
65 mdio_mux_sandbox_mark_selection(dev, priv->sel); in mdio_mux_sandbox_deselect()
[all …]
A Dmdio_mux_i2creg.c25 static int mdio_mux_i2creg_select(struct udevice *mux, int cur, int sel) in mdio_mux_i2creg_select() argument
31 if (cur == sel) in mdio_mux_i2creg_select()
35 val = (val_old & ~priv->mask) | (sel & priv->mask); in mdio_mux_i2creg_select()
/u-boot/drivers/video/nexell/soc/
A Ds5pxx18_soc_disptop.c64 regvalue = (benb << 31) | (sel << 0); in nx_disp_top_set_resconvmux()
68 void nx_disp_top_set_hdmimux(int benb, u32 sel) in nx_disp_top_set_hdmimux() argument
74 regvalue = (benb << 31) | (sel << 0); in nx_disp_top_set_hdmimux()
84 regvalue = (benb << 31) | (sel << 0); in nx_disp_top_set_mipimux()
94 regvalue = (benb << 31) | (sel << 0); in nx_disp_top_set_lvdsmux()
98 void nx_disp_top_set_primary_mux(u32 sel) in nx_disp_top_set_primary_mux() argument
103 writel((u32)sel, &pregister->tftmpu_mux); in nx_disp_top_set_primary_mux()
106 void nx_disp_top_hdmi_set_vsync_start(u32 sel) in nx_disp_top_hdmi_set_vsync_start() argument
111 writel((u32)sel, &pregister->hdmisyncctrl0); in nx_disp_top_hdmi_set_vsync_start()
127 writel((u32)sel, &pregister->hdmisyncctrl1); in nx_disp_top_hdmi_set_hactive_start()
[all …]
A Ds5pxx18_soc_disptop.h354 void nx_disp_top_set_resconvmux(int benb, u32 sel);
355 void nx_disp_top_set_hdmimux(int benb, u32 sel);
356 void nx_disp_top_set_mipimux(int benb, u32 sel);
357 void nx_disp_top_set_lvdsmux(int benb, u32 sel);
358 void nx_disp_top_set_primary_mux(u32 sel);
359 void nx_disp_top_hdmi_set_vsync_start(u32 sel);
361 void nx_disp_top_hdmi_set_hactive_start(u32 sel);
362 void nx_disp_top_hdmi_set_hactive_end(u32 sel);
/u-boot/drivers/power/regulator/
A Dstpmic1.c53 if (sel >= range->min_sel && sel <= range->max_sel) in stpmic1_output_find_uv()
142 int sel; in stpmic1_buck_get_uv() local
145 if (sel < 0) in stpmic1_buck_get_uv()
146 return sel; in stpmic1_buck_get_uv()
148 sel &= STPMIC1_BUCK_VOUT_MASK; in stpmic1_buck_get_uv()
164 if (sel < 0) in stpmic1_buck_set_value()
165 return sel; in stpmic1_buck_set_value()
317 if (sel < 0) in stpmic1_ldo_get_value()
318 return sel; in stpmic1_ldo_get_value()
343 if (sel < 0) in stpmic1_ldo_set_value()
[all …]
A Dbd71837.c76 .sel_mask = (sel) \
248 if (!val || sel < r->min_sel || sel > r->max_sel) in vrange_find_value()
251 *val = r->min_volt + r->step * (sel - r->min_sel); in vrange_find_value()
256 unsigned int *sel) in vrange_find_selector() argument
267 *sel = r->min_sel; in vrange_find_selector()
320 unsigned int sel; in bd71837_set_value() local
340 found = !vrange_find_selector(r, uvolt, &sel); in bd71837_set_value()
349 found = !vrange_find_value(r, sel, &tmp); in bd71837_set_value()
359 sel <<= ffs(plat->volt_mask) - 1; in bd71837_set_value()
362 sel |= range; in bd71837_set_value()
[all …]
A Dtps65910_regulator.c143 int sel, val, vout; in tps65910_regulator_get_value() local
150 sel = (val & TPS65910_SEL_MASK) >> 2; in tps65910_regulator_get_value()
151 vout = (vin >= *(rgp->vin_min + sel)) ? *(rgp->vout + sel) : 0; in tps65910_regulator_get_value()
196 int sel = 0; in tps65910_regulator_set_value() local
201 if (uV == *(ldo->vout + sel)) in tps65910_regulator_set_value()
203 } while (++sel < VOUT_CHOICE_COUNT); in tps65910_regulator_set_value()
204 if (sel == VOUT_CHOICE_COUNT) in tps65910_regulator_set_value()
206 if (pdata->supply < *(ldo->vin_min + sel)) in tps65910_regulator_set_value()
213 val |= sel << 2; in tps65910_regulator_set_value()
/u-boot/arch/arm/mach-exynos/
A Dclock.c650 sel = (sel >> 24) & 0xf; in exynos4_get_pwm_clk()
711 sel = (sel >> (dev_index << 2)) & 0xf; in exynos4_get_uart_clk()
713 if (sel == 0x6) in exynos4_get_uart_clk()
757 sel = (sel >> (dev_index << 2)) & 0xf; in exynos4x12_get_uart_clk()
759 if (sel == 0x6) in exynos4x12_get_uart_clk()
793 sel = (sel >> (dev_index << 2)) & 0xf; in exynos4_get_mmc_clk()
795 if (sel == 0x6) in exynos4_get_mmc_clk()
926 sel = sel & 0xf; in exynos4_get_lcd_clk()
968 sel = sel & 0xf; in exynos5_get_lcd_clk()
1013 if (sel) in exynos5420_get_lcd_clk()
[all …]
/u-boot/drivers/video/nexell/
A Ds5pxx18_dp_rgb.c20 int rsc = 0, sel = 0; in rgb_switch() local
24 sel = mpu ? 1 : 0; in rgb_switch()
27 sel = rsc ? 3 : 2; in rgb_switch()
34 nx_disp_top_set_primary_mux(sel); in rgb_switch()
/u-boot/net/
A Dmdio-mux-uclass.c47 int sel; member
63 static int mmux_change_sel(struct udevice *ch, bool sel) in mmux_change_sel() argument
71 if (sel) { in mmux_change_sel()
72 err = ops->select(mux, priv->selected, ch_data->sel); in mmux_change_sel()
76 priv->selected = ch_data->sel; in mmux_change_sel()
79 ops->deselect(mux, ch_data->sel); in mmux_change_sel()
152 ch_data->sel = dev_read_u32_default(ch, "reg", MDIO_MUX_SELECT_NONE); in dm_mdio_mux_child_post_bind()
154 if (ch_data->sel == MDIO_MUX_SELECT_NONE) in dm_mdio_mux_child_post_bind()
/u-boot/arch/mips/include/asm/
A Dmipsregs.h1317 if (sel == 0) \
1335 else if (sel == 0) \
1366 if (sel == 0) \
1383 else if (sel == 0) \
1443 if (sel == 0) \
1476 else if (sel == 0) \
1523 : "i" (sel)); \
1975 : "i" (sel)); \
1988 : "i" (sel)); \
2001 "i" (sel)); \
[all …]
/u-boot/arch/arm/cpu/armv7/bcm281xx/
A Dclk-core.c122 if (selector_exists(&cd->sel)) { in peri_clk_enable()
123 reg = readl(base + cd->sel.offset); in peri_clk_enable()
124 bitfield_replace(reg, cd->sel.shift, cd->sel.width, in peri_clk_enable()
125 c->sel); in peri_clk_enable()
126 writel(reg, base + cd->sel.offset); in peri_clk_enable()
193 c->sel = i; in peri_clk_set_rate()
217 if (selector_exists(&cd->sel)) { in peri_clk_get_rate()
218 reg = readl(base + cd->sel.offset); in peri_clk_get_rate()
219 c->sel = bitfield_extract(reg, cd->sel.shift, cd->sel.width); in peri_clk_get_rate()
225 c->sel = 0; in peri_clk_get_rate()
[all …]
A Dclk-bcm281xx.c150 .sel = SELECTOR(0x0a28, 0, 3),
162 .sel = SELECTOR(0x0a2c, 0, 3),
174 .sel = SELECTOR(0x0a34, 0, 3),
186 .sel = SELECTOR(0x0a30, 0, 3),
239 .sel = SELECTOR(0x0a64, 0, 3),
250 .sel = SELECTOR(0x0a68, 0, 3),
261 .sel = SELECTOR(0x0a84, 0, 3),
/u-boot/arch/arm/cpu/armv7/bcm235xx/
A Dclk-core.c122 if (selector_exists(&cd->sel)) { in peri_clk_enable()
123 reg = readl(base + cd->sel.offset); in peri_clk_enable()
124 bitfield_replace(reg, cd->sel.shift, cd->sel.width, in peri_clk_enable()
125 c->sel); in peri_clk_enable()
126 writel(reg, base + cd->sel.offset); in peri_clk_enable()
193 c->sel = i; in peri_clk_set_rate()
217 if (selector_exists(&cd->sel)) { in peri_clk_get_rate()
218 reg = readl(base + cd->sel.offset); in peri_clk_get_rate()
219 c->sel = bitfield_extract(reg, cd->sel.shift, cd->sel.width); in peri_clk_get_rate()
225 c->sel = 0; in peri_clk_get_rate()
[all …]
A Dclk-bcm235xx.c150 .sel = SELECTOR(0x0a28, 0, 3),
162 .sel = SELECTOR(0x0a2c, 0, 3),
174 .sel = SELECTOR(0x0a34, 0, 3),
186 .sel = SELECTOR(0x0a30, 0, 3),
239 .sel = SELECTOR(0x0a64, 0, 3),
250 .sel = SELECTOR(0x0a68, 0, 3),
261 .sel = SELECTOR(0x0a84, 0, 3),
/u-boot/include/power/
A Dstpmic1.h38 #define STPMIC1_BUCK_VOUT(sel) (sel << STPMIC1_BUCK_VOUT_SHIFT) argument
53 #define STPMIC1_LDO_VOUT(sel) (sel << STPMIC1_LDO12356_VOUT_SHIFT) argument
/u-boot/drivers/net/phy/
A Datheros.c198 int sel; in ar803x_of_init() local
254 sel = AR803x_CLK_25M_25MHZ_XTAL; in ar803x_of_init()
257 sel = AR803x_CLK_25M_50MHZ_PLL; in ar803x_of_init()
260 sel = AR803x_CLK_25M_62_5MHZ_PLL; in ar803x_of_init()
263 sel = AR803x_CLK_25M_125MHZ_PLL; in ar803x_of_init()
273 priv->clk_25m_reg |= FIELD_PREP(AR803x_CLK_25M_MASK, sel); in ar803x_of_init()
289 sel = AR803x_CLK_25M_DR_FULL; in ar803x_of_init()
292 sel = AR803x_CLK_25M_DR_HALF; in ar803x_of_init()
295 sel = AR803x_CLK_25M_DR_QUARTER; in ar803x_of_init()
304 priv->clk_25m_reg |= FIELD_PREP(AR803x_CLK_25M_DR_MASK, sel); in ar803x_of_init()
/u-boot/arch/arm/dts/
A Dk3-am65-main.dtsi270 ti,otap-del-sel-sd-hs = <0x0>;
271 ti,otap-del-sel-sdr12 = <0x0>;
272 ti,otap-del-sel-sdr25 = <0x0>;
273 ti,otap-del-sel-sdr50 = <0x8>;
275 ti,otap-del-sel-ddr50 = <0x5>;
276 ti,otap-del-sel-ddr52 = <0x5>;
277 ti,otap-del-sel-hs200 = <0x5>;
278 ti,otap-del-sel-hs400 = <0x0>;
281 ti,itap-del-sel-sdr12 = <0xa>;
283 ti,clkbuf-sel = <0x7>;
[all …]
A Dk3-j7200-common-proc-board-u-boot.dtsi119 cpsw-phy-sel@40f04040 {
120 compatible = "ti,am654-cpsw-phy-sel";
122 reg-names = "gmii-sel";
/u-boot/arch/arm/mach-kirkwood/
A Dmpp.c55 unsigned int sel = MPP_SEL(*mpp_list); in kirkwood_mpp_conf() local
79 mpp_ctrl[num / 8] |= sel << shift; in kirkwood_mpp_conf()
/u-boot/arch/arm/mach-tegra/
A Dcpu.c236 struct clk_pll_table *sel; in init_pllx() local
256 sel = &tegra_pll_x_table[chip_sku][osc]; in init_pllx()
257 pllx_set_rate(pll, sel->n, sel->m, sel->p, sel->cpcon); in init_pllx()
/u-boot/scripts/
A Dget_maintainer.pl1739 my $sel = "";
1817 if ($sel eq "y") {
1825 } elsif ($sel eq "*" || $sel eq '^') {
1831 } elsif ($sel eq "0") {
1835 } elsif ($sel eq "t") {
1857 } elsif ($sel eq "a") {
1867 } elsif ($sel eq "s") {
1877 } elsif ($sel eq "o") {
1880 } elsif ($sel eq "g") {
1887 } elsif ($sel eq "b") {
[all …]
/u-boot/arch/mips/cpu/
A Dstart.S29 .macro init_wr sel
30 MTC0 zero, CP0_WATCHLO,\sel
31 mtc0 t1, CP0_WATCHHI,\sel
32 mfc0 t0, CP0_WATCHHI,\sel
/u-boot/board/freescale/ls1043ardb/
A Dls1043ardb_pbi.cfg9 #USB PHY frequency sel
/u-boot/board/freescale/ls1043aqds/
A Dls1043aqds_pbi.cfg9 #USB PHY frequency sel

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