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Searched refs:shift (Results 1 – 25 of 280) sorted by relevance

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/u-boot/drivers/clk/meson/
A Dclk_meson.h29 u8 shift; member
34 #define SETPMASK(width, shift) GENMASK(shift + width - 1, shift) argument
35 #define CLRPMASK(width, shift) (~SETPMASK(width, shift)) argument
37 #define PARM_GET(width, shift, reg) \ argument
38 (((reg) & SETPMASK(width, shift)) >> (shift))
39 #define PARM_SET(width, shift, reg, val) \ argument
40 (((reg) & CLRPMASK(width, shift)) | ((val) << (shift)))
/u-boot/include/
A Dbitfield.h43 static inline uint bitfield_mask(uint shift, uint width) in bitfield_mask() argument
45 return ((1 << width) - 1) << shift; in bitfield_mask()
49 static inline uint bitfield_extract(uint reg_val, uint shift, uint width) in bitfield_extract() argument
51 return (reg_val & bitfield_mask(shift, width)) >> shift; in bitfield_extract()
58 static inline uint bitfield_replace(uint reg_val, uint shift, uint width, in bitfield_replace() argument
61 uint mask = bitfield_mask(shift, width); in bitfield_replace()
63 return (reg_val & ~mask) | ((bitfield_val << shift) & mask); in bitfield_replace()
75 uint shift = bitfield_shift(mask); in bitfield_extract_by_mask() local
77 return (reg_val & mask) >> shift; in bitfield_extract_by_mask()
87 uint shift = bitfield_shift(mask); in bitfield_replace_by_mask() local
[all …]
A Dsandbox-clk.h46 void __iomem *reg, u8 shift, in sandbox_clk_divider() argument
50 reg, shift, width, 0); in sandbox_clk_divider()
69 void __iomem *reg, u8 shift) in sandbox_clk_gate2() argument
72 CLK_SET_RATE_PARENT, reg, shift, in sandbox_clk_gate2()
77 u8 shift, u8 width, in sandbox_clk_mux() argument
82 CLK_SET_RATE_NO_REPARENT, reg, shift, in sandbox_clk_mux()
/u-boot/drivers/clk/imx/
A Dclk.h61 shift, 0x3, 0); in imx_clk_gate2()
69 reg, shift, 0x3, 0); in imx_clk_gate4()
78 reg, shift, 0x3, 0); in imx_clk_gate4_flags()
92 reg, shift, width, 0); in imx_clk_divider()
100 reg, shift, width, 0); in imx_clk_busy_divider()
108 reg, shift, width, 0); in imx_clk_divider2()
135 reg, shift, width, 0); in imx_clk_mux2_flags()
163 reg, shift, width, 0); in imx_clk_mux2()
170 shift, 0, NULL); in imx_clk_gate()
177 shift, 0, NULL); in imx_clk_gate_flags()
[all …]
/u-boot/arch/x86/lib/
A Ddiv64.c19 u64 __ashldi3(u64 num, unsigned int shift) in __ashldi3() argument
24 if (shift >= 32) { in __ashldi3()
28 if (!shift) in __ashldi3()
31 (output.words.lower >> (32 - shift)); in __ashldi3()
32 output.words.lower = output.words.lower << shift; in __ashldi3()
37 u64 __lshrdi3(u64 num, unsigned int shift) in __lshrdi3() argument
42 if (shift >= 32) { in __lshrdi3()
46 if (!shift) in __lshrdi3()
48 output.words.lower = output.words.lower >> shift | in __lshrdi3()
49 (output.words.higher << (32 - shift)); in __lshrdi3()
[all …]
/u-boot/arch/arm/mach-uniphier/bcu/
A Dbcu-ld4.c17 int shift; in uniphier_ld4_bcu_init() local
26 shift = bd->dram_ch[0].size / 0x04000000 * 4; in uniphier_ld4_bcu_init()
27 writel(ch(shift), BCIPPCCHR2); /* 0x80000000-0x9fffffff */ in uniphier_ld4_bcu_init()
29 shift -= 32; in uniphier_ld4_bcu_init()
30 writel(ch(shift), BCIPPCCHR3); /* 0xa0000000-0xbfffffff */ in uniphier_ld4_bcu_init()
32 shift -= 32; in uniphier_ld4_bcu_init()
33 writel(ch(shift), BCIPPCCHR4); /* 0xc0000000-0xdfffffff */ in uniphier_ld4_bcu_init()
/u-boot/arch/mips/mach-mtmips/
A Dddr_cal.c76 int maxval, int shift, u32 regval) in dqs_find_max() argument
82 dqsval = regval | (fieldval << shift); in dqs_find_max()
91 int minval, int shift, u32 regval) in dqs_find_min() argument
97 dqsval = regval | (fieldval << shift); in dqs_find_min()
111 u32 dqs_dly_tmp, dqs_dly, test_dqs, shift; in ddr_calibrate() local
146 shift = i * 8; in ddr_calibrate()
147 dqs_dly &= ~(0xff << shift); in ddr_calibrate()
150 dqs_dly_tmp = dqs_dly | (0xf << shift); in ddr_calibrate()
152 0xf, 4 + shift, dqs_dly_tmp); in ddr_calibrate()
157 shift, dqs_dly_tmp); in ddr_calibrate()
[all …]
/u-boot/arch/arm/dts/
A Domap3xxx-clocks.dtsi28 ti,bit-shift = <6>;
39 ti,bit-shift = <7>;
88 ti,bit-shift = <4>;
102 ti,bit-shift = <2>;
116 ti,bit-shift = <6>;
143 ti,bit-shift = <2>;
248 ti,bit-shift = <16>;
355 ti,bit-shift = <6>;
363 ti,bit-shift = <8>;
390 ti,bit-shift = <5>;
[all …]
A Domap34xx-omap36xx-clocks.dtsi23 ti,bit-shift = <3>;
32 ti,bit-shift = <2>;
40 ti,bit-shift = <1>;
48 ti,bit-shift = <0>;
55 ti,bit-shift = <0>;
65 ti,bit-shift = <0>;
73 ti,bit-shift = <1>;
89 ti,bit-shift = <4>;
121 ti,bit-shift = <7>;
137 ti,bit-shift = <6>;
[all …]
A Ddra7xx-clocks.dtsi258 ti,bit-shift = <23>;
332 ti,bit-shift = <23>;
370 ti,bit-shift = <23>;
408 ti,bit-shift = <23>;
457 ti,bit-shift = <23>;
483 ti,bit-shift = <23>;
557 ti,bit-shift = <23>;
756 ti,bit-shift = <4>;
1196 ti,bit-shift = <8>;
1248 ti,bit-shift = <7>;
[all …]
A Dam35xx-clocks.dtsi16 ti,bit-shift = <1>;
24 ti,bit-shift = <9>;
32 ti,bit-shift = <2>;
40 ti,bit-shift = <10>;
48 ti,bit-shift = <0>;
56 ti,bit-shift = <8>;
64 ti,bit-shift = <3>;
73 ti,bit-shift = <4>;
93 ti,bit-shift = <23>;
101 ti,bit-shift = <23>;
A Domap3-igep0020-u-boot.dtsi15 reg-shift = <2>;
19 reg-shift = <2>;
23 reg-shift = <2>;
A Domap36xx-am35xx-omap3430es2plus-clocks.dtsi50 ti,bit-shift = <1>;
112 ti,bit-shift = <0>;
120 ti,bit-shift = <0>;
128 ti,bit-shift = <1>;
136 ti,bit-shift = <2>;
144 ti,bit-shift = <2>;
167 ti,bit-shift = <0>;
177 ti,bit-shift = <0>;
185 ti,bit-shift = <1>;
193 ti,bit-shift = <0>;
[all …]
/u-boot/drivers/misc/
A Dpca9551_led.c43 u8 shift, buf; in pca9551_led_get_state() local
50 shift = led << 1; in pca9551_led_get_state()
53 shift = (led - 4) << 1; in pca9551_led_get_state()
60 *state = (buf >> shift) & 0x03; in pca9551_led_get_state()
67 u8 shift, buf, mask; in pca9551_led_set_state() local
74 shift = led << 1; in pca9551_led_set_state()
77 shift = (led - 4) << 1; in pca9551_led_set_state()
79 mask = 0x03 << shift; in pca9551_led_set_state()
85 buf = (buf & ~mask) | ((state & 0x03) << shift); in pca9551_led_set_state()
/u-boot/drivers/pinctrl/nxp/
A Dpinctrl-mxs.c50 int muxsel = MUXID_TO_MUXSEL(val), shift; in mxs_pinctrl_set_mux() local
55 shift = pin % 16 * 2; in mxs_pinctrl_set_mux()
102 int pinid, bank, pin, shift; in mxs_pinctrl_set_state() local
123 shift = pin % 8 * 4; in mxs_pinctrl_set_state()
124 mxs_pinctrl_rmwl(ma, 0x3, shift, reg); in mxs_pinctrl_set_state()
129 shift = pin % 8 * 4 + 2; in mxs_pinctrl_set_state()
131 writel(1 << shift, reg + SET); in mxs_pinctrl_set_state()
133 writel(1 << shift, reg + CLR); in mxs_pinctrl_set_state()
140 shift = pin; in mxs_pinctrl_set_state()
142 writel(1 << shift, reg + SET); in mxs_pinctrl_set_state()
[all …]
/u-boot/arch/arm/mach-imx/mx7ulp/
A Dscg.c57 u32 shift, mask; in scg_sircdiv_get_rate() local
81 val = (reg & mask) >> shift; in scg_sircdiv_get_rate()
95 u32 shift, mask; in scg_fircdiv_get_rate() local
119 val = (reg & mask) >> shift; in scg_fircdiv_get_rate()
133 u32 shift, mask; in scg_soscdiv_get_rate() local
157 val = (reg & mask) >> shift; in scg_soscdiv_get_rate()
171 u32 shift, mask, gate, valid; in scg_apll_pfd_get_rate() local
208 val = (reg & mask) >> shift; in scg_apll_pfd_get_rate()
221 u32 shift, mask, gate, valid; in scg_spll_pfd_get_rate() local
258 val = (reg & mask) >> shift; in scg_spll_pfd_get_rate()
[all …]
/u-boot/drivers/clk/
A Dclk-mux.c93 val >>= mux->shift; in clk_mux_get_parent()
133 reg = mux->mask << (mux->shift + 16); in clk_mux_set_parent()
140 reg &= ~(mux->mask << mux->shift); in clk_mux_set_parent()
142 val = val << mux->shift; in clk_mux_set_parent()
161 void __iomem *reg, u8 shift, u32 mask, in clk_hw_register_mux_table() argument
171 if (width + shift > 16) { in clk_hw_register_mux_table()
188 mux->shift = shift; in clk_hw_register_mux_table()
218 void __iomem *reg, u8 shift, u32 mask, in clk_register_mux_table() argument
224 flags, reg, shift, mask, clk_mux_flags, in clk_register_mux_table()
234 void __iomem *reg, u8 shift, u8 width, in clk_register_mux() argument
[all …]
A Dclk-divider.c85 val >>= divider->shift; in clk_divider_recalc_rate()
166 val = clk_div_mask(divider->width) << (divider->shift + 16); in clk_divider_set_rate()
169 val &= ~(clk_div_mask(divider->width) << divider->shift); in clk_divider_set_rate()
171 val |= (u32)value << divider->shift; in clk_divider_set_rate()
184 void __iomem *reg, u8 shift, u8 width, in _register_divider() argument
192 if (width + shift > 16) { in _register_divider()
205 div->shift = shift; in _register_divider()
228 void __iomem *reg, u8 shift, u8 width, in clk_register_divider() argument
233 clk = _register_divider(dev, name, parent_name, flags, reg, shift, in clk_register_divider()
/u-boot/arch/arm/mach-kirkwood/
A Dmpp.c57 int shift; in kirkwood_mpp_conf() local
70 shift = (num & 7) << 2; in kirkwood_mpp_conf()
73 sel_save = (mpp_ctrl[num / 8] >> shift) & 0xf; in kirkwood_mpp_conf()
78 mpp_ctrl[num / 8] &= ~(0xf << shift); in kirkwood_mpp_conf()
79 mpp_ctrl[num / 8] |= sel << shift; in kirkwood_mpp_conf()
/u-boot/drivers/gpio/
A Dhsdk-creg-gpio.c25 u8 shift; member
34 u8 reg_shift = oft * hcg->bit_per_gpio + hcg->shift; in hsdk_creg_gpio_set_value()
67 val >>= oft * hcg->bit_per_gpio + hcg->shift; in hsdk_creg_gpio_get_value()
83 u32 shift, bit_per_gpio, activate, deactivate, gpio_count; in hsdk_creg_gpio_probe() local
88 shift = dev_read_u32_default(dev, "gpio-first-shift", 0); in hsdk_creg_gpio_probe()
112 if ((gpio_count * bit_per_gpio + shift) > 32) { in hsdk_creg_gpio_probe()
114 uc_priv->bank_name, gpio_count * bit_per_gpio + shift); in hsdk_creg_gpio_probe()
140 hcg->shift = (u8)shift; in hsdk_creg_gpio_probe()
/u-boot/include/linux/
A Dmath64.h150 static inline u64 mul_u64_u32_shr(u64 a, u32 mul, unsigned int shift) in mul_u64_u32_shr() argument
152 return (u64)(((unsigned __int128)a * mul) >> shift); in mul_u64_u32_shr()
157 static inline u64 mul_u64_u64_shr(u64 a, u64 mul, unsigned int shift) in mul_u64_u64_shr() argument
159 return (u64)(((unsigned __int128)a * mul) >> shift); in mul_u64_u64_shr()
174 ret = mul_u32_u32(al, mul) >> shift; in mul_u64_u32_shr()
176 ret += mul_u32_u32(ah, mul) << (32 - shift); in mul_u64_u32_shr()
183 static inline u64 mul_u64_u64_shr(u64 a, u64 b, unsigned int shift) in mul_u64_u64_shr() argument
218 if (shift == 0) in mul_u64_u64_shr()
220 if (shift < 64) in mul_u64_u64_shr()
221 return (rl.ll >> shift) | (rh.ll << (64 - shift)); in mul_u64_u64_shr()
[all …]
/u-boot/drivers/clk/at91/
A Dclk-peripheral.c159 u32 val, shift = ffs(periph->layout->div_mask) - 1; in clk_sam9x5_peripheral_get_rate() local
167 shift = (val & periph->layout->div_mask) >> shift; in clk_sam9x5_peripheral_get_rate()
169 return parent_rate >> shift; in clk_sam9x5_peripheral_get_rate()
176 int shift; in clk_sam9x5_peripheral_set_rate() local
191 for (shift = 0; shift <= PERIPHERAL_MAX_SHIFT; shift++) { in clk_sam9x5_peripheral_set_rate()
192 if (parent_rate >> shift <= rate) in clk_sam9x5_peripheral_set_rate()
195 if (shift == PERIPHERAL_MAX_SHIFT + 1) in clk_sam9x5_peripheral_set_rate()
202 (shift << (ffs(periph->layout->div_mask) - 1)) | in clk_sam9x5_peripheral_set_rate()
205 return parent_rate >> shift; in clk_sam9x5_peripheral_set_rate()
/u-boot/drivers/clk/ti/
A Dclk.c23 void clk_ti_latch(fdt_addr_t reg, s8 shift) in clk_ti_latch() argument
27 if (shift < 0) in clk_ti_latch()
30 latch = 1 << shift; in clk_ti_latch()
/u-boot/drivers/net/qe/
A Duccf.c53 *shift = 16; in ucc_get_cmxucr_reg()
58 *shift = 0; in ucc_get_cmxucr_reg()
63 *shift = 16; in ucc_get_cmxucr_reg()
68 *shift = 0; in ucc_get_cmxucr_reg()
73 *shift = 16; in ucc_get_cmxucr_reg()
78 *shift = 0; in ucc_get_cmxucr_reg()
83 *shift = 16; in ucc_get_cmxucr_reg()
88 *shift = 0; in ucc_get_cmxucr_reg()
99 u8 shift = 0; in ucc_set_clk_src() local
286 clk_bits <<= shift; in ucc_set_clk_src()
[all …]
/u-boot/drivers/qe/
A Duccf.c54 *shift = 16; in ucc_get_cmxucr_reg()
59 *shift = 0; in ucc_get_cmxucr_reg()
64 *shift = 16; in ucc_get_cmxucr_reg()
69 *shift = 0; in ucc_get_cmxucr_reg()
74 *shift = 16; in ucc_get_cmxucr_reg()
79 *shift = 0; in ucc_get_cmxucr_reg()
84 *shift = 16; in ucc_get_cmxucr_reg()
89 *shift = 0; in ucc_get_cmxucr_reg()
100 u8 shift = 0; in ucc_set_clk_src() local
287 clk_bits <<= shift; in ucc_set_clk_src()
[all …]

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