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Searched refs:slcr_base (Results 1 – 5 of 5) sorted by relevance

/u-boot/arch/arm/mach-zynq/
A Dslcr.c92 writel(SLCR_LOCK_MAGIC, &slcr_base->slcr_lock); in zynq_slcr_lock()
120 clrbits_le32(&slcr_base->reboot_status, 0xF000000); in zynq_slcr_cpu_reset()
122 writel(1, &slcr_base->pss_rst_ctrl); in zynq_slcr_cpu_reset()
132 writel(0xF, &slcr_base->fpga_rst_ctrl); in zynq_slcr_devcfg_disable()
135 reg_val = readl(&slcr_base->lvl_shftr_en); in zynq_slcr_devcfg_disable()
137 writel(reg_val, &slcr_base->lvl_shftr_en); in zynq_slcr_devcfg_disable()
140 writel(0xA, &slcr_base->lvl_shftr_en); in zynq_slcr_devcfg_disable()
150 writel(0xF, &slcr_base->lvl_shftr_en); in zynq_slcr_devcfg_enable()
153 writel(0x0, &slcr_base->fpga_rst_ctrl); in zynq_slcr_devcfg_enable()
161 return readl(&slcr_base->boot_mode); in zynq_slcr_get_boot_mode()
[all …]
A Dcpu.c61 writel(0x1F, &slcr_base->ocm_cfg); in arch_cpu_init()
63 writel(0x0, &slcr_base->fpga_rst_ctrl); in arch_cpu_init()
65 writel(0x0, &slcr_base->ddr_urgent_sel); in arch_cpu_init()
67 writel(0xC, &slcr_base->ddr_urgent); in arch_cpu_init()
/u-boot/drivers/clk/
A Dclk_zynq.c62 return &slcr_base->arm_pll_ctrl; in zynq_clk_get_register()
64 return &slcr_base->ddr_pll_ctrl; in zynq_clk_get_register()
66 return &slcr_base->io_pll_ctrl; in zynq_clk_get_register()
70 return &slcr_base->smc_clk_ctrl; in zynq_clk_get_register()
72 return &slcr_base->pcap_clk_ctrl; in zynq_clk_get_register()
74 return &slcr_base->sdio_clk_ctrl; in zynq_clk_get_register()
76 return &slcr_base->uart_clk_ctrl; in zynq_clk_get_register()
78 return &slcr_base->spi_clk_ctrl; in zynq_clk_get_register()
81 return &slcr_base->dci_clk_ctrl; in zynq_clk_get_register()
95 return &slcr_base->can_clk_ctrl; in zynq_clk_get_register()
[all …]
/u-boot/arch/arm/mach-zynqmp/include/mach/
A Dhardware.h89 #define slcr_base ((struct iou_slcr_regs *)ZYNQMP_IOU_SLCR_BASEADDR) macro
/u-boot/arch/arm/mach-zynq/include/mach/
A Dhardware.h85 #define slcr_base ((struct slcr_regs *)ZYNQ_SYS_CTRL_BASEADDR) macro

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