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/u-boot/scripts/dtc/pylibfdt/
A DMakefile26 $(obj)/_libfdt.so: $(src)/setup.py $(PYLIBFDT_srcs) FORCE
29 rm -f $(obj)/_libfdt*.so
32 always += _libfdt.so
34 clean-files += libfdt.i _libfdt.so libfdt.py libfdt_wrap.c
/u-boot/doc/device-tree-bindings/clock/
A Drockchip,rk3399-dmc.txt4 - rockchip,cru: this driver should access cru regs, so need get cru here
5 - rockchip,pmucru: this driver should access pmucru regs, so need get pmucru here
6 - rockchip,pmugrf: this driver should access pmugrf regs, so need get pmugrf here
7 - rockchip,pmusgrf: this driver should access pmusgrf regs, so need get pmusgrf here
8 - rockchip,cic: this driver should access cic regs, so need get cic here
A Drockchip,rk3288-dmc.txt4 - rockchip,cru: this driver should access cru regs, so need get cru here
5 - rockchip,grf: this driver should access grf regs, so need get grf here
6 - rockchip,pmu: this driver should access pmu regs, so need get pmu here
7 - rockchip,sgrf: this driver should access sgrf regs, so need get sgrf here
8 - rockchip,noc: this driver should access noc regs, so need get noc here
18 -logic-supply: this driver should adjust VDD_LOGIC according to dmc frequency, so need get logic-su…
/u-boot/scripts/
A DMakefile.host53 host-cshobjs := $(sort $(foreach m,$(host-cshlib),$($(m:.so=-objs))))
54 host-cxxshobjs := $(sort $(foreach m,$(host-cxxshlib),$($(m:.so=-objs))))
152 $(addprefix $(obj)/,$($(@F:.so=-objs))) \
156 $(call multi_depend, $(host-cshlib), .so, -objs)
162 $(addprefix $(obj)/,$($(@F:.so=-objs))) \
166 $(call multi_depend, $(host-cxxshlib), .so, -objs)
/u-boot/scripts/kconfig/tests/new_choice_with_dep/
A DKconfig18 This is a new symbol, so should be asked.
35 This is a new symbol, so should be asked.
/u-boot/doc/
A DREADME.silent11 so this will make the value in the flash env take effect at
20 "stderr" are set to "nulldev", so subsequent messages are
24 - When booting a linux kernel, the "bootargs" are fixed up so that
A DREADME.davinci.nand_spl9 functions, so we can write the UBL header and the spl
27 pagesize = 0x800, so the u-boot.ubl image (which you get with:
62 * so we can define, how many UBL Headers
78 Headers, so you have to burn the UBL header page from the u-boot.ubl
133 In the UBL block, I can set the page to values != 0, so it
135 flash, but the RBL ignores the page settings, so I have to
A DREADME.watchdog9 new code, so it must be serviced, but the board would rather it
30 TODO: vision2 is removed now, so perhaps this can be changed.
A DREADME.bloblist10 a central structure. Each record of information is assigned a tag so that its
22 reading an SoC register. Reading the register may reset the value, so that it
66 bloblist in preparation for the next stage. This involves adding a checksum so
68 bloblist is in use, changes can be made which will affect the checksum, so it
A DREADME.sata19 Notes: Hard disk sectors are normally 512 bytes, so
50 U-Boot doesn't support writing to an ext2 file system, so the
A DREADME.fsl-dpaa9 so we introduce CONFIG_FSL_FM_10GEC_REGULAR_NOTATION to identify the new SoCs on
/u-boot/lib/efi_loader/
A D.gitignore2 *.so
/u-boot/lib/efi_selftest/
A D.gitignore3 *.so
/u-boot/scripts/kconfig/tests/auto_submenu/
A DKconfig10 This depends on A, so should be a submenu of A.
49 This depends on A, but not a consecutive item, so can/should not
/u-boot/board/congatec/
A DKconfig22 Note that PCIE_ECAM_BASE is set up by the FSP so the value used
33 Note that PCIE_ECAM_BASE is set up by the FSP so the value used
/u-boot/board/dfi/
A DKconfig20 Note that PCIE_ECAM_BASE is set up by the FSP so the value used
33 Note that PCIE_ECAM_BASE is set up by the FSP so the value used
/u-boot/test/
A Dnokia_rx51_test.sh108 cp -a libc6_2.5.1/lib/ld-linux.so.3 rootfs/lib/
109 cp -a libc6_2.5.1/lib/ld-2.5.so rootfs/lib/
110 cp -a libc6_2.5.1/lib/libc.so.6 rootfs/lib/
111 cp -a libc6_2.5.1/lib/libc-2.5.so rootfs/lib/
112 cp -a libc6_2.5.1/lib/libcrypt.so.1 rootfs/lib/
113 cp -a libc6_2.5.1/lib/libcrypt-2.5.so rootfs/lib/
/u-boot/arch/x86/cpu/
A Du-boot-spl.lds48 * Force 32-byte alignment so that it lines up with the start of
52 * The alignment of BSS depends on what is in it, so can range
/u-boot/doc/board/google/
A Dchromebook_coral.rst8 Intel Apollo Lake platform (APL). The 'reef' Chromebooks use the same APL SoC so
28 start16 region, so the TPL image must be 30KB at most, and CONFIG_TPL_TEXT_BASE
30 move from f800 to fe00, providing another 1.5KB, but TPL is only about 19KB so
40 TPL operates without CONFIG_TPL_PCI enabled so PCI config access must use the
42 device so that PCI devices are bound by driver model. Then arch_cpu_init_tpl()
71 PCI auto-config is not used in SPL either, but CONFIG_SPL_PCI is defined, so
73 used. However PCI auto-config is not used so the same static memory mapping set
103 defined, so proper PCI access is available. The same static memory mapping set
129 that probes PCI after relocation is the serial port, in initr_serial(), so FSP-S
131 using the SPI driver, to avoid probing PCI and causing an autoconfig, so
/u-boot/tools/binman/test/
A D074_vblock.dts22 * Put this after the vblock so that its contents are not
/u-boot/doc/device-tree-bindings/pmic/
A Dpm8916.txt3 This PMIC is connected using SPMI bus so should be child of SPMI bus controller.
/u-boot/board/intel/minnowmax/
A DKconfig24 # Enable Winbond so we can use Dediprog em100pro emulator which does
/u-boot/drivers/usb/cdns3/
A DKconfig28 Host controller is compliant with XHCI so it will use
49 Host controller is compliant with XHCI so it will use
/u-boot/board/google/chromebox_panther/
A DKconfig18 # Panther actually uses haswell, not ivybridge, so this is just a placeholder
/u-boot/arch/x86/include/asm/acpi/
A Dpcr.asl52 * for all ports so that the callers don't need the per-port knowledge
76 * for all ports so that the callers don't need the per-port knowledge

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